參數(shù)資料
型號: MC8641VU1000NE
廠商: Freescale Semiconductor
文件頁數(shù): 57/130頁
文件大?。?/td> 0K
描述: IC MPU SGL CORE E600 1023FCCBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC86xx
處理器類型: 32-位 MPC86xx PowerPC
速度: 1.0GHz
電壓: 0.95V
安裝類型: 表面貼裝
封裝/外殼: 994-BCBGA,F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝: 994-FCCBGA(33x33)
包裝: 托盤
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
32
Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Timing diagrams for FIFO appear in Figure 8 and Figure 9.
.
Figure 8. FIFO Transmit AC Timing Diagram
Figure 9. FIFO Receive AC Timing Diagram
8.2.2
GMII AC Timing Specifications
This section describes the GMII transmit and receive AC timing specifications.
8.2.2.1
GMII Transmit AC Timing Specifications
Table 28 provides the GMII transmit AC timing specifications.
Table 28. GMII Transmit AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
GMII data TXD[7:0], TX_ER, TX_EN setup time
tGTKHDV
2.5
ns
GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay
tGTKHDX
0.5
5.0
ns
GTX_CLK data clock rise time (20%-80%)
tGTXR
2
——
1.0
ns
tFIT
tFITH
tFITF
tFITDX
TXD[7:0]
TX_EN
GTX_CLK
TX_ER
tFITDV
tFITR
tFIR
tFIRH
tFIRF
tFIRR
RX_CLK
RXD[7:0]
RX_DV
RX_ER
valid data
tFIRDX
tFIRDV
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