參數(shù)資料
型號: MC8640THX1067NE
廠商: Freescale Semiconductor
文件頁數(shù): 105/130頁
文件大?。?/td> 0K
描述: IC DUAL CORE PROCESSOR 994-CBGA
標準包裝: 1
系列: MPC86xx
處理器類型: 32-位 MPC86xx PowerPC
速度: 1.067GHz
電壓: 0.95V
安裝類型: 表面貼裝
封裝/外殼: 994-BCBGA,F(xiàn)CCBGA
供應商設備封裝: 994-FCCBGA(33x33)
包裝: 托盤
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
76
Freescale Semiconductor
Serial RapidIO
To ensure interoperability between drivers and receivers of different vendors and technologies, AC
coupling at the receiver input must be used.
15.1
DC Requirements for Serial RapidIO SD
n_REF_CLK and
SD
n_REF_CLK
For more information, see Section 13.2, “SerDes Reference Clocks.”
15.2
AC Requirements for Serial RapidIO SD
n_REF_CLK and
SD
n_REF_CLK
Table 51 lists AC requirements.
15.3
Signal Definitions
LP-Serial links use differential signaling. This section defines terms used in the description and
specification of differential signals. Figure 53 shows how the signals are defined. The figures show
waveforms for either a transmitter output (TD and TD) or a receiver input (RD and RD). Each signal
swings between A volts and B volts where A > B. Using these waveforms, the definitions are as follows:
1. The transmitter output signals and the receiver input signals TD, TD, RD and RD each have a
peak-to-peak swing of A – B volts
2. The differential output signal of the transmitter, VOD, is defined as VTD –VTD
3. The differential input signal of the receiver, VID, is defined as VRD –VRD
4. The differential output signal of the transmitter and the differential input signal of the receiver
each range from A – B to –(A – B) volts
Table 51. SD
n_REF_CLK and SDn_REF_CLK AC Requirements
Symbol
Parameter Description
Min
Typical
Max
Units
Comments
tREF
REFCLK cycle time
10(8)
ns
8 ns applies only to serial RapidIO
with 125-MHz reference clock
tREFCJ
REFCLK cycle-to-cycle jitter. Difference in the
period of any two adjacent REFCLK cycles
80
ps
tREFPJ
Phase jitter. Deviation in edge location with
respect to mean edge location
–40
40
ps
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