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| 型號(hào)： | MC80F0224Q |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁(yè)數(shù)： | 45/128頁(yè) |
| 文件大小： | 1408K |
| 代理商： | MC80F0224Q |
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Preliminary
MC80F0208/16/24
MAR. 2005 Ver 0.2
41
11. BASIC INTERVAL TIMER
The MC80F0208/16/24 has one 8-bit Basic Interval Timer that is
free-run and can not stop. Block diagram is shown in Figure 11-
1. In addition, the Basic Interval Timer generates the time base
for watchdog timer counting. It also provides a Basic interval tim-
er interrupt (BITIF).
The 8-bit Basic interval timer register (BITR) is increased every
internal count pulse which is divided by prescaler. Since prescal-
er has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024
of the oscillator frequency. As the count overflow from FFH to
00H, this overflow causes the interrupt to be generated. The Basic
Interval Timer is controlled by the clock control register
(CKCTLR) shown in Figure 10-2.
When write "1" to bit BTCL of CKCTLR, BITR register is
cleared to "0" and restart to count-up. The bit BTCL becomes "0"
after one machine cycle by hardware.
If the STOP instruction executed after writing "1" to bit RCWDT
of CKCTLR, it goes into the internal RC oscillated watchdog tim-
er mode. In this mode, all of the block is halted except the internal
RC oscillator, Basic Interval Timer and Watchdog Timer. More
detail informations are explained in Power Saving Function. The
bit WDTON decides Watchdog Timer or the normal 7-bit timer.
Source clock can be selected by lower 3 bits of CKCTLR.
BITR and CKCTLR are located at same address, and address
0F2
H
is read as a BITR, and written to CKCTLR.
Figure 11-1 Block Diagram of Basic Interval Timer
Table 11-1 Basic Interval Timer Interrupt Period
MUX
Basic Interval
Timer Interrupt
BITR
Select Input clock 3
Basic Interval Timer
clock control register
source
clock
8-bit up-counter
BTS[2:0]
BTCL
÷
1024
÷
512
÷
256
÷
128
÷
64
÷
32
÷
16
÷
8
To Watchdog timer (WDTCK)
CKCTLR
clear
overflow
Internal bus line
[0F2
H
]
[0F2
H
]
BITIF
Read
X
IN
PIN
P
Internal RC OSC
RCWDT
1
0
RCWDT
CKCTLR
[2:0]
Source clock
Interrupt (overflow) Period (ms)
@ f
XIN
= 8MHz
000
001
010
011
100
101
110
111
f
XIN
÷
8
f
XIN
÷
16
f
XIN
÷
32
f
XIN
÷
64
f
XIN
÷
128
f
XIN
÷
256
f
XIN
÷
512
f
XIN
÷
1024
0.256
0.512
1.024
2.048
4.096
8.192
16.384
32.768
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