參數資料
型號： ADUC7060BSTZ32
廠商： Analog Devices Inc
文件頁數： 101/108頁
文件大小： 0K
描述： IC MCU FLASH 24BIT 32KB 48LQFP
產品培訓模塊： Process Control
Weigh Scale Introduction
產品變化通告： ADuC7060/1 Idd Specification Change 01/Feb/2010
設計資源： 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
Low power, Long Range, ISM Wireless Measuring Node (CN0164)
標準包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 10MHz
連通性： I²C，SPI，UART/USART
外圍設備： POR，PWM，溫度傳感器，WDT
輸入/輸出數： 14
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 1K x 32
電壓 - 電源 (Vcc/Vdd)： 2.375 V ~ 2.625 V
數據轉換器： A/D 5x24b，8x24b，D/A 1x14b
振蕩器型： 內部
工作溫度： -40°C ~ 125°C
封裝/外殼： 48-LQFP
包裝： 托盤
產品目錄頁面： 739 (CN2011-ZH PDF)
ADuC7060/ADuC7061
Data Sheet
Rev. D | Page 92 of 108
Table 104. I2CSCON MMR Bit Designations
Bit
Name
Description
15:11
Reserved bits.
10
I2CSTXENI
Slave transmit interrupt enable bit.
Set this bit to enable an interrupt after a slave transmits a byte.
Clear this interrupt source.
9
I2CSRXENI
Slave receive interrupt enable bit.
Set this bit to enable an interrupt after the slave receives data.
Clear this interrupt source.
8
I2CSSENI
I2C stop condition detected interrupt enable bit.
Set this bit to enable an interrupt on detecting a stop condition on the I2C bus.
Clear this interrupt source.
7
I2CNACKEN
I2C no acknowledge enable bit.
Set this bit to no acknowledge the next byte in the transmission sequence.
Clear this bit to let the hardware control the acknowledge/no acknowledge sequence.
6
I2CSSEN
I2C slave SCL stretch enable bit.
Set this bit to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low until
I2CSSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling edge.
Clear this bit to disable clock stretching.
5
I2CSETEN
I2C early transmit interrupt enable bit.
Setting this bit enables a transmit request interrupt just after the positive edge of SCL during the read bit
transmission.
Clear this bit to enable a transmit request interrupt just after the negative edge of SCL during the read bit
transmission.
4
I2CGCCLR
I2C general call status and ID clear bit.
Writing a 1 to this bit clears the general call status and ID bits in the I2CSSTA register.
Clear this bit at all other times.
3
I2CHGCEN
Hardware general call enable. When this bit and Bit 2 are set, and having received a general call (Address 0x00)
and a data byte, the device checks the contents of the I2CALT against the receive register. If the contents match,
the device has received a hardware general call. This is used if a device needs urgent attention from a master
device without knowing which master it needs to turn to. This is a “to whom it may concern” call. The ADuC706x
watches for these addresses. The device that requires attention embeds its own address into the message. All
masters listen, and the one that can handle the device contacts its slave and acts appropriately. The LSB of the
I2CALT register should always be written to 1, as per the I2C January 2000 bus specification.
2
I2CGCEN
General call enable bit. Set this bit to enable the slave device to acknowledge an I2C general call, Address 0x00
(write). The device then recognizes a data bit. If it receives a 0x06 (reset and write programmable part of the slave
address by hardware) as the data byte, the I2C interface resets as per the I2C January 2000 bus specification. This
command can be used to reset an entire I2C system. If it receives a 0x04 (write programmable part of the slave
address by hardware) as the data byte, the general call interrupt status bit sets on any general call. The user must
take corrective action by reprogramming the device address.
1
ADR10EN
I2C 10-bit address mode.
Set to 1 to enable 10-bit address mode.
Clear to 0 to enable normal address mode.
0
I2CSEN
I2C slave enable bit.
Set by user to enable I2C slave mode.
Clear to disable I2C slave mode.
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