參數(shù)資料
型號: MC80C52XXX-36
廠商: TEMIC SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CDIP40
封裝: SIDE BRAZED, 40 PIN
文件頁數(shù): 14/132頁
文件大小: 10886K
代理商: MC80C52XXX-36
184
ATmega8535(L)
2502K–AVR–10/06
The TWAR should be loaded with the 7-bit slave address (in the seven most significant
bits of TWAR) to which the TWI will respond when programmed as a Slave Transmitter
or Receiver, and not needed in the Master modes. In multimaster systems, TWAR must
be set in masters which can be addressed as slaves by other masters.
The LSB of TWAR is used to enable recognition of the general call address (0x00).
There is an associated address comparator that looks for the slave address (or general
call address if enabled) in the received serial address. If a match is found, an interrupt
request is generated.
Bits 7..1 – TWA: TWI (Slave) Address Register
These seven bits constitute the slave address of the TWI unit.
Bit 0 – TWGCE: TWI General Call Recognition Enable Bit
If set, this bit enables the recognition of a General Call given over the Two-wire Serial
Bus.
Read/Write
R/W
Initial Value
1111
111
0
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