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| 型號(hào)： | MC80C32-36SHXXX |
| 廠(chǎng)商： | TEMIC SEMICONDUCTORS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 36 MHz, MICROCONTROLLER, CDIP40 |
| 文件頁(yè)數(shù)： | 67/83頁(yè) |
| 文件大小： | 8336K |
| 代理商： | MC80C32-36SHXXX |
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8
8021G–AVR–03/11
ATmega329P/3290P
2.3.12
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in ”System and Reset
Characteristics” on page 336. Shorter pulses are not guaranteed to generate a reset.
2.3.13
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.3.14
XTAL2
Output from the inverting Oscillator amplifier.
2.3.15
AVCC
AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con-
nected to V
CC, even if the ADC is not used. If the ADC is used, it should be connected to VCC
through a low-pass filter.
2.3.16
AREF
This is the analog reference pin for the A/D Converter.
2.3.17
LCDCAP
An external capacitor (typical > 470nF) must be connected to the LCDCAP pin as shown in Fig-
ure 23-2, if the LCD module is enabled and configured to use internal power. This capacitor acts
as a reservoir for LCD power (V
LCD). A large capacitance reduces ripple on VLCD but increases
the time until V
LCD reaches its target value.
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