參數(shù)資料
型號: MC74VHC74
廠商: ON SEMICONDUCTOR
英文描述: Dual D Type Flip Flop with Set and Reset(雙上升沿D觸發(fā)器(有預置和清除端))
中文描述: 雙D型拖鞋(雙上升沿?觸發(fā)器的設置和復位(有預置和清除端))
文件頁數(shù): 2/6頁
文件大小: 100K
代理商: MC74VHC74
MC74VHC74
http://onsemi.com
2
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
Derating — SOIC Packages: – 7 mW/ C from 65 to 125 C
TSSOP Package: 6.1 mW/ C from 65 to 125 C
V
DC Supply Voltage
– 0.5 to + 7.0
mA
mA
mA
mW
V
V
DC Output Voltage
– 0.5 to V
+ 0.5
V
I
Output Diode Current
20
I
DC Output Current, per Pin
I
DC Supply Current, V
and GND Pins
25
P
Power Dissipation in Still Air,
50
T
stg
Storage Temperature
SOIC Packages
TSSOP Package
500
450
– 65 to + 150
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
5.5
5.5
V
CC
+ 85
100
Unit
V
CC
V
in
V
out
T
A
t
r
, t
f
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Operating Temperature, All Package Types
Input Rise and Fall Time
2.0
0
0
40
0
V
V
V
C
V
CC
= 3.3V
±
0.3V
CC
ns/V
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
V
CC
T
A
= 25
°
C
0 to 5.5
T
A
= 40 to 85
°
C
Unit
Min
Typ
Max
3.0
Min
Max
IL
1.50
1.50
CC
Output Voltage
I
OH
= 50 A
3.0
2.9
0.0
2.9
I
OH
= 4mA
OH
2.48
OL
in
IH
IL
4.5
0.1
0.1
V
in
= V
IH
or V
IL
I
OL
= 8mA
4.5
0.36
0.44
I
in
CC
Maximum Input
in
CC
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
(V
in
or V
out
)
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
V
CC
.
SD1
CP1
D1
RD1
11
12
13
14
8
9
10
5
4
3
2
1
7
6
SD2
CP2
D2
RD2
V
CC
Q2
Q2
GND
Q1
Q1
Figure 2. PIN ASSIGNMENT
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