參數資料
型號: MC74LVX157MG
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: Quad 2-Channel Multiplexe With 5 V−Tolerant Inputs
中文描述: LV/LV-A/LVX/H SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16
封裝: LEAD FREE, EIAJ, SO-16
文件頁數: 4/6頁
文件大小: 101K
代理商: MC74LVX157MG
MC74LVX157
http://onsemi.com
4
The specification applies to any outputs switching in the same direction, either HIGHtoLOW (t
OSHL
) or LOWtoHIGH (t
OSLH
); parameter
Symbol
t
,
PHL
L
Typ
L
C
11.6
21.1
Parameter
Test Conditions
Min
Max
t
PHL
7.6
12.5
1.0
15.5
ns
V
CC
L
C
11.4
20.4
5.1
11.4
1.0
7.9
1.0
24.0
13.0
t
PHL
C
L
V
= 3.3
0.3V
C
= 15pF
L
7.0
11.0
1.0
13.0
PLH
Propagation Delay, E to Zn
V
CC
9.7
15.0
9.1
1.0
17.6
1.0
17.0
24.0
C
L
= 50pF
t
OSHL
OutputtoOutput Skew (Note 1)
V
CC
= 2.7V
C
L
1.5
1.5
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/4 (per bit). C
PD
is used to determine the noload
dynamic power consumption; P
D
= C
PD
V
CC2
f
in
+ I
CC
V
CC
.
A
Typ
A
Min
NOISE CHARACTERISTICS
(Input t
r
= t
f
= 3.0ns, C
L
= 50pF, V
CC
= 3.3V, Measured in SOIC Package)
T
A
= 25
°
C
Typ
Symbol
Characteristic
Max
Unit
V
OLP
V
OLV
V
IHD
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum High Level Dynamic Input Voltage
0.3
0.5
V
0.3
0.5
V
2.0
V
V
ILD
Maximum Low Level Dynamic Input Voltage
0.8
V
In or S
E
t
PLH
t
PHL
V
CC
GND
50%
50% V
CC
Zn
V
CC
GND
Zn
t
PHL
t
PLH
50%
50% V
CC
*Includes all probe and jig capacitance
Figure 5. Propagation Delay Test Circuit
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 3.
Figure 4.
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