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參數(shù)資料
| 型號(hào)： | MC74LVX04M |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | Power Factor Correction (PFC) and PWM Controller Combo; Package: DIP; No of Pins: 16; Container: Rail |
| 中文描述： | LV/LV-A/LVX/H SERIES, HEX 1-INPUT INVERT GATE, PDSO14 |
| 封裝： | EIAJ, SOIC-14 |
| 文件頁(yè)數(shù)： | 3/5頁(yè) |
| 文件大?。?/td> | 132K |
| 代理商： | MC74LVX04M |
MC74LVX04
LCX DATA
BR1339 — REV 3
3
MOTOROLA
b l
di i
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (tOSHL) or LOW–to–HIGH (tOSLH); parameter
guaranteed by design.
U i
tPHL
tPLH,
7.9
13.6
1.0
16.0
6.6
9.7
1.0
11.0
VCC = 2.7V
1.5
1.5
ns
b l
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR
)
= CPD VCC fin + ICC/6 (per buffer). CPD s used to determine the no–load
dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
U i
NOISE CHARACTERISTICS
(Input tr = tf = 3.0ns, CL = 50pF, VCC = 3.3V, Measured in SOIC Package)
Symbol
b l
Characteristic
i i
TA = 25
°
C
Typ
U i
Unit
Max
VOLP
VOLV
VIHD
VILD
Quiet Output Maximum Dynamic VOL
Quiet Output Minimum Dynamic VOL
Minimum High Level Dynamic Input Voltage
0.3
0.5
V
–0.3
–0.5
V
2.0
V
Maximum Low Level Dynamic Input Voltage
0.8
V
Figure 3. Switching Waveforms
VCC
GND
50%
50% VCC
A
O
tPHL
tPLH
* Includes all probe and jig capacitance
Figure 4. Test Circuit
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
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