參數(shù)資料
型號: MC74LVX00MEL
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: Quad 2-Input NAND Gate With 5 V−Tolerant Inputs
中文描述: LV/LV-A/LVX/H SERIES, QUAD 2-INPUT NAND GATE, PDSO14
封裝: EIAJ, SOIC-14
文件頁數(shù): 4/6頁
文件大?。?/td> 92K
代理商: MC74LVX00MEL
MC74LVX00
http://onsemi.com
4
The specification applies to any outputs switching in the same direction, either HIGHtoLOW (t
OSHL
) or LOWtoHIGH (t
OSLH
); parameter
guaranteed by design.
Symbol
C
L
= 50 pF
13.6
1.0
Parameter
Test Conditions
Min
4.1
6.6
Typ
t
(Note 1)
t
PHL
V
= 3.3
±
0.3 V
Output
V
CC
= 3.3
±
0.3 V
7.9
1.0
7.5
16.0
C
L
= 15 pF
L
6.2
OSHL
OutputtoOutput Skew
V
CC
L
C
1.5
2. C
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/4 (per gate). C
PD
is used to determine the
noload dynamic power consumption; P
D
= C
PD
V
CC2
f
in
+ I
CC
V
CC
.
CAPACITIVE CHARACTERISTICS
Symbol
T
A
= 25
°
C
T
A
= 40 to 85
°
C
Parameter
Min
Typ
Max
Min
Max
Unit
Cin
Input Capacitance
4
10
10
pF
C
PD
Power Dissipation Capacitance (Note 2)
19
pF
NOISE CHARACTERISTICS
(Input t
r
= t
f
= 3.0 ns, C
L
= 50 pF, V
CC
= 3.3 V, Measured in SOIC Package)
T
A
= 25
°
C
Symbol
Characteristic
Typ
Max
Unit
V
OLP
Quiet Output Maximum Dynamic V
OL
0.3
0.5
V
V
OLV
Quiet Output Minimum Dynamic V
OL
0.3
0.5
V
V
IHD
Minimum High Level Dynamic Input Voltage
2.0
V
V
ILD
Maximum Low Level Dynamic Input Voltage
0.8
V
Figure 3. Switching Waveforms
V
CC
GND
50%
50% V
CC
A or B
O
t
PHL
t
PLH
*Includes all probe and jig capacitance
Figure 4. Test Circuit
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
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