參數(shù)資料
型號: MC74LCX16543A
廠商: Motorola, Inc.
英文描述: LOW-VOLTAGE CMOS 16-BIT LATCHING TRANSCEIVER
中文描述: 低電壓CMOS 16位磁收發(fā)器
文件頁數(shù): 1/8頁
文件大?。?/td> 136K
代理商: MC74LCX16543A
SEMICONDUCTOR TECHNICAL DATA
1
REV 0
Motorola, Inc. 1997
1/97
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The MC74LCX16543A is a high performance, non–inverting 16–bit
latching transceiver operating from a 2.7 to 3.6V supply. The device is
byte controlled. Each byte has separate control inputs which can be tied
together for full 16–bit operation. High impedance TTL compatible inputs
significantly reduce current loading to input drivers while TTL compatible
outputs offer improved switching noise performance. A VI specification of
5.5V allows MC74LCX16543A inputs to be safely driven from 5V devices.
The MC74LCX16543A is suitable for memory address driving and all TTL
level bus oriented transceiver applications.
For data flow from A to B with the EAB LOW, the A–to–B Output
Enable (OEAB) must be LOW in order to enable data to the B bus, as
indicated in the Function Table. With EAB LOW, a LOW signal on the
A–to–B Latch Enable (LEAB) input makes the A–to–B latches
transparent; a subsequent LOW–to–HIGH transition of the LEAB signal
will latch the A latches, and the outputs no longer change with the A
inputs. With EAB and OEAB both LOW, the 3–State B output buffers are
active and reflect the data present at the output of the A latches. Control
of data flow from B to A is symmetric to that above, but uses the EBA,
LEBA, and OEBA inputs.
Designed for 2.7 to 3.6V VCC Operation
5.2ns Maximum tpd
5V Tolerant — Interface Capability With 5V TTL Logic
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0V
LVTTL Compatible
LVCMOS Compatible
24mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current in All Three Logic States (20
μ
A)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds 500mA
ESD Performance: Human Body Model >2000V; Machine Model >200V
DT SUFFIX
56–LEAD PLASTIC TSSOP PACKAGE
CASE 1202–01
LOW–VOLTAGE CMOS
16–BIT LATCHING
TRANSCEIVER
PIN NAMES
Function
Output Enable Inputs
Enable Inputs
Latch Enable Inputs
3–State Inputs/Outputs
3–State Inputs/Outputs
Pins
OExxn
Exxn
LExxn
A0–A15
B0–B15
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