參數(shù)資料
型號: MC74HCT374AN
廠商: ON Semiconductor
文件頁數(shù): 1/8頁
文件大?。?/td> 0K
描述: IC FLIP FLOP OCT D 3ST 20-DIP
產(chǎn)品變化通告: LTB Notification 03/Jan/2008
標準包裝: 18
系列: 74HCT
功能: 標準
類型: D 型總線
輸出類型: 三態(tài)非反相
元件數(shù): 1
每個元件的位元數(shù): 8
頻率 - 時鐘: 30MHz
延遲時間 - 傳輸: 31ns
觸發(fā)器類型: 正邊沿
輸出電流高,低: 6mA,6mA
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -55°C ~ 125°C
安裝類型: 通孔
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
Semiconductor Components Industries, LLC, 2011
May, 2011 Rev. 11
1
Publication Order Number:
MC74HCT374A/D
MC74HCT374A
Octal 3-State Noninverting
D Flip-Flop with
LSTTL-Compatible Inputs
HighPerformance SiliconGate CMOS
The MC74HCT374A may be used as a level converter for
interfacing TTL or NMOS outputs to HighSpeed CMOS inputs.
The HCT374A is identical in pinout to the LS374.
Data meeting the setup and hold time is clocked to the outputs with
the rising edge of Clock. The Output Enable does not affect the state of
the flipflops, but when Output Enable is high, the outputs are forced
to the highimpedance state. Thus, data may be stored even when the
outputs are not enabled.
The HCT374A is identical in function to the HCT574A, which has
the input pins on the opposite side of the package from the output pins.
This device is similar in function to the HCT534A, which has
inverting outputs.
Features
Output Drive Capability: 15 LSTTL Loads
TTL/NMOSCompatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 mA
In Compliance With the JEDEC Standard No. 7.0 A Requirements
Chip Complexity: 276 FETs or 69 Equivalent Gates
Improvements over HCT374
— Improved Propagation Delays
— 50% Lower Quiescent Power
— Improved Input Noise and Latchup Immunity
These Devices are PbFree and are RoHS Compliant
http://onsemi.com
MARKING
DIAGRAMS
HCT
374A
ALYWG
G
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
20
1
HCT374A
AWLYYWWG
PDIP20
N SUFFIX
CASE 738
1
20
1
20
MC74HCT374AN
AWLYYWWG
20
1
74HCT374A
AWLYYWWG
20
1
SOEIAJ20
F SUFFIX
CASE 967
SOIC20
DW SUFFIX
CASE 751D
TSSOP20
DT SUFFIX
CASE 948E
1
20
1
20
1
20
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G
= PbFree Package
(Note: Microdot may be in either location)
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