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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MC74HC595ADR2 |
| 寤犲晢锛� | ON Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 8/12闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC SHIFT REGISTR 8BIT 3ST 16SOIC |
| 妯欐簴鍖呰锛� | 1 |
| 绯诲垪锛� | 74HC |
| 閭忚集椤炲瀷锛� | 绉讳綅瀵勫瓨鍣� |
| 杓稿嚭椤炲瀷锛� | 涓夋厠(t脿i) |
| 鍏冧欢鏁�(sh霉)锛� | 1 |
| 姣忓€嬪厓浠剁殑浣嶅厓鏁�(sh霉)锛� | 8 |
| 鍔熻兘锛� | 涓茶鑷冲苟琛� |
| 闆绘簮闆诲锛� | 2 V ~ 6 V |
| 宸ヤ綔婧害锛� | -55°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 16-SOIC锛�0.154"锛�3.90mm 瀵級 |
| 渚涙噳鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 16-SOIC |
| 鍖呰锛� | 妯欐簴鍖呰 |
| 鍏跺畠鍚嶇ū锛� | MC74HC595ADR2ODKR MC74HC595ADR2ODKR-ND MC74HC595ADR2OSDKR |
MC74HC595A
http://onsemi.com
5
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
Unit
Guaranteed Limit
VCC
V
Parameter
Symbol
Unit
v 125_C
v 85_C
鈥� 55 to 25_C
VCC
V
Parameter
tTLH,
tTHL
Maximum Output Transition Time, QA QH
(Figures 3 and 7)
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
31
18
15
ns
tTLH,
tTHL
Maximum Output Transition Time, SQH
(Figures 1 and 7)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
Cin
Maximum Input Capacitance
鈥�
10
pF
Cout
Maximum ThreeState Output Capacitance (Output in
HighImpedance State), QA QH
鈥�
15
pF
CPD
Power Dissipation Capacitance (Per Package)*
Typical @ 25掳C, VCC = 5.0 V
pF
300
TIMING REQUIREMENTS (Input tr = tf = 6.0 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
25_C to 鈥�55_C
v 85_C
v 125_C
tsu
Minimum Setup Time, Serial Data Input A to Shift Clock
(Figure 5)
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
tsu
Minimum Setup Time, Shift Clock to Latch Clock
(Figure 6)
2.0
3.0
4.5
6.0
75
60
15
13
95
70
19
16
110
80
22
19
ns
th
Minimum Hold Time, Shift Clock to Serial Data Input A
(Figure 5)
2.0
3.0
4.5
6.0
5.0
ns
trec
Minimum Recovery Time, Reset Inactive to Shift Clock
(Figure 2)
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
tw
Minimum Pulse Width, Reset
(Figure 2)
2.0
3.0
4.5
6.0
60
45
12
10
75
60
15
13
90
70
18
15
ns
tw
Minimum Pulse Width, Shift Clock
(Figure 1)
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
tw
Minimum Pulse Width, Latch Clock
(Figure 6)
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
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| MC74HC595ADR2G | 鍔熻兘鎻忚堪:瑷堟暩(sh霉)鍣ㄧЩ浣嶅瘎瀛樺櫒 8-Bit 3 State Shift RoHS:鍚� 鍒堕€犲晢:Texas Instruments 瑷堟暩(sh霉)鍣ㄩ鍨�: 瑷堟暩(sh霉)闋嗗簭:Serial to Serial/Parallel 闆昏矾鏁�(sh霉)閲�:1 灏佽 / 绠遍珨:SOIC-20 Wide 閭忚集绯诲垪: 閭忚集椤炲瀷: 杓稿叆绶氳矾鏁�(sh霉)閲�:1 杓稿嚭椤炲瀷:Open Drain 鍌虫挱寤堕伈鏅傞枔:650 ns 鏈€澶у伐浣滄韩搴�:+ 125 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽:Reel |
| MC74HC595ADR2G-CUT TAPE | 鍒堕€犲晢:ON 鍔熻兘鎻忚堪:MC74HC595A Series 2 to 6 V Shift Register w/ 3 State Outputs - SOIC-16 |
| MC74HC595ADR2H | 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪: 鍒堕€犲晢:ON Semiconductor 鍔熻兘鎻忚堪: |
| MC74HC595ADT | 鍔熻兘鎻忚堪:瑷堟暩(sh霉)鍣ㄧЩ浣嶅瘎瀛樺櫒 8-Bit 3 State Shift RoHS:鍚� 鍒堕€犲晢:Texas Instruments 瑷堟暩(sh霉)鍣ㄩ鍨�: 瑷堟暩(sh霉)闋嗗簭:Serial to Serial/Parallel 闆昏矾鏁�(sh霉)閲�:1 灏佽 / 绠遍珨:SOIC-20 Wide 閭忚集绯诲垪: 閭忚集椤炲瀷: 杓稿叆绶氳矾鏁�(sh霉)閲�:1 杓稿嚭椤炲瀷:Open Drain 鍌虫挱寤堕伈鏅傞枔:650 ns 鏈€澶у伐浣滄韩搴�:+ 125 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽:Reel |
| MC74HC595ADTG | 鍔熻兘鎻忚堪:瑷堟暩(sh霉)鍣ㄧЩ浣嶅瘎瀛樺櫒 8-Bit 3 State Shift RoHS:鍚� 鍒堕€犲晢:Texas Instruments 瑷堟暩(sh霉)鍣ㄩ鍨�: 瑷堟暩(sh霉)闋嗗簭:Serial to Serial/Parallel 闆昏矾鏁�(sh霉)閲�:1 灏佽 / 绠遍珨:SOIC-20 Wide 閭忚集绯诲垪: 閭忚集椤炲瀷: 杓稿叆绶氳矾鏁�(sh霉)閲�:1 杓稿嚭椤炲瀷:Open Drain 鍌虫挱寤堕伈鏅傞枔:650 ns 鏈€澶у伐浣滄韩搴�:+ 125 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽:Reel |
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