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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MC74HC4020AD |
| 寤犲晢锛� | ON Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 8/12闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC COUNTER 14STAGE BIN 16-SOIC |
| 鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� | LTB Notification 03/Jan/2008 |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 48 |
| 绯诲垪锛� | 74HC |
| 閭忚集椤炲瀷锛� | 浜岄€�(j矛n)鍒惰▓(j矛)鏁�(sh霉)鍣� |
| 鏂瑰悜锛� | 涓� |
| 鍏冧欢鏁�(sh霉)锛� | 1 |
| 姣忓€�(g猫)鍏冧欢鐨勪綅鍏冩暩(sh霉)锛� | 14 |
| 寰�(f霉)浣嶏細 | 鐣版 |
| 瑷�(j矛)鏁�(sh霉)閫熺巼锛� | 50MHz |
| 瑙哥櫦(f膩)鍣ㄩ鍨嬶細 | 璨�(f霉)閭婃部 |
| 闆绘簮闆诲锛� | 2 V ~ 6 V |
| 宸ヤ綔婧害锛� | -55°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 16-SOIC锛�0.154"锛�3.90mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 16-SOIC |
| 鍖呰锛� | 绠′欢 |
MC74HC4020A
http://onsemi.com
5
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
55 to 25掳C
鈮�85掳C
鈮�125掳C
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
3.0
4.5
6.0
10
15
30
50
9.0
14
28
50
8.0
12
25
40
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q1*
(Figures 1 and 4)
2.0
3.0
4.5
6.0
96
63
31
25
106
71
36
30
115
88
40
35
ns
tPHL
Maximum Propagation Delay, Reset to Any Q
(Figures 2 and 4)
2.0
3.0
4.5
6.0
65
30
26
72
36
35
32
90
40
35
ns
tPLH,
tPHL
Maximum Propagation Delay, Qn to Qn+1
(Figures 3 and 4)
2.0
3.0
4.5
6.0
69
40
17
14
80
45
21
15
90
50
28
22
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
19
ns
Cin
Maximum Input Capacitance
10
pF
* For TA = 25掳C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:
VCC = 2.0 V: tP = [93.7 + 59.3 (n1)] ns
VCC = 4.5 V: tP = [30.25 + 14.6 (n1)] ns
VCC = 3.0 V: tP = [61.5 + 34.4 (n1)] ns
VCC = 6.0 V: tP = [24.4 + 12 (n1)] ns
CPD
Power Dissipation Capacitance (Per Package)*
Typical @ 25掳C, VCC = 5.0 V
pF
38
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