參數(shù)資料
型號: MC74HC367ADTR2
廠商: ON SEMICONDUCTOR
元件分類: 總線收發(fā)器
英文描述: HC/UH SERIES, 6-BIT DRIVER, TRUE OUTPUT, PDSO16
封裝: PLASTIC, TSSOP-16
文件頁數(shù): 3/6頁
文件大小: 190K
代理商: MC74HC367ADTR2
MC74HC367A
http://onsemi.com
3
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Unit
Guaranteed Limit
VCC
V
Test Conditions
Parameter
Symbol
Unit
v 125_C
v 85_C
– 55 to
25_C
VCC
V
Test Conditions
Parameter
Symbol
VOL
Maximum LowLevel Output
Voltage
Vin = VIL
|Iout| v 20 μA
2.0
4.5
6.0
0.1
0.1
0.1
V
Vin = VIL
|Iout| v 3.6 mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
3.0
4.5
6.0
0.26
0.33
0.40
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
μA
IOZ
Maximum ThreeState
Leakage Current
Output in HighImpedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
± 0.5
± 5.0
± 10
μA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 μA
6.0
4
40
160
μA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
– 55 to
25_C
v 85_C
v 125_C
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
2.0
3.0
4.5
6.0
120
60
24
20
150
75
30
26
180
90
36
31
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
2.0
3.0
4.5
6.0
175
90
35
30
220
110
44
37
265
135
53
45
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
2.0
3.0
4.5
6.0
190
95
38
32
240
120
48
21
285
150
57
48
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
3.0
4.5
6.0
60
22
12
10
75
28
15
13
90
34
18
15
ns
Cin
Maximum Input Capacitance
10
10
10
pF
Cout
Maximum ThreeState Output Capacitance
(Output in HighImpedance State)
15
15
15
pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Buffer)*
Typical @ 25°C, VCC = 5.0 V
pF
60
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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