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參數(shù)資料
| 型號： | MC74HC259D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-Bit Addressable Latch 1-of-8 Decoder |
| 中文描述： | HC/UH SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO16 |
| 封裝： | PLASTIC, SOIC-16 |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 199K |
| 代理商： | MC74HC259D |
MC54/74HC259
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
tPHL
(Figures 1 and 6)
4.5
37
56
6.0
37
46
55
tPLH,
Maximum Propagation Delay, Enable to Output
2.0
200
250
46
300
ns
(Figures 4 and 6)
4.5
31
47
6.0
13
39
19
Cin
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Maximum Input Capacitance
—
10
16
10
pF
10
CPD
Power Dissipation Capacitance (Per Package)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
30
pF
(Figure 5)
4.5
20
30
(Figure 5)
4.5
6.0
5
5
25
tw
Minimum Pulse Width, Reset or Enable
2.0
6.0
80
14
100
5
5
120
20
5
5
ns
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
1000
500
1000
500
17
1000
500
ns
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