AC ELECTRICAL CHARACTERISTICS (CL
參數(shù)資料
型號(hào): MC74HC251ADTG
廠商: ON Semiconductor
文件頁數(shù): 4/9頁
文件大?。?/td> 0K
描述: IC DATA SEL/MUX 3ST 8X1 16TSSOP
標(biāo)準(zhǔn)包裝: 96
系列: 74HC
類型: 數(shù)據(jù)選擇器/多路復(fù)用器
電路: 1 x 8:1
獨(dú)立電路: 1
輸出電流高,低: 5.2mA,5.2mA
電壓電源: 單電源
電源電壓: 2 V ~ 6 V
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
MC74HC251A
http://onsemi.com
4
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
55 to
25°C
v 85°C
v 125°C
tPLH,
tPHL
Maximum Propagation Delay, Input D to Output Y or Y
(Figures 2, 3 and 6)
2.0
4.5
6.0
185
37
31
230
46
39
280
56
48
ns
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y or Y
(Figures 3 and 6)
2.0
4.5
6.0
205
41
35
255
51
43
310
62
53
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 5 and 7)
2.0
4.5
6.0
195
39
33
245
49
42
295
59
50
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 5 and 7)
2.0
4.5
6.0
145
29
25
180
36
31
220
44
38
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 5 and 7)
2.0
4.5
6.0
220
44
37
275
55
47
330
66
56
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 5 and 7)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 2 and 6)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Cin
Maximum Input Capacitance
10
pF
Cout
Maximum ThreeState Output Capacitance
(Output in HighImpedance State)
15
pF
CPD
Power Dissipation Capacitance (Per Package)
Typical @ 25°C, VCC = 5.0 V
pF
36
PIN DESCRIPTIONS
INPUTS
D0, D1, …, D7 (Pins 4, 3, 2, 1, 15, 14, 13, 12)
Data inputs. Data on one of these eight binary inputs may
be selected to appear on the output.
CONTROL INPUTS
A0, A1, A2 (Pins 11, 10, 9)
Address inputs. The data on these pins are the binary
address of the selected input (see the Function Table).
Output Enable (Pin 7)
Output Enable. This input pin must be at a low level for
the selected data to appear at the outputs. If the Output
Enable pin is high, both the Y and Y outputs are taken to the
highimpedance state.
OUTPUTS
Y, Y (Pins 5, 6)
Data outputs. The selected data is presented at these pins
in both true (Y output) and complemented (Y output) forms.
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