
MC54/74HC241A
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
4
SWITCHING WAVEFORMS
Figure 1.
Figure 2.
* Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 3. Test Circuit
* Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 4. Test Circuit
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
1 k
ENABLE A
ENABLE B
OUTPUT Y
OUTPUT Y
VCC
GND
VCC
GND
HIGH
IMPEDANCE
HIGH
IMPEDANCE
VOL
VOH
50%
50%
50%
50%
90%
10%
tPZL
tPLZ
tPZH
tPHZ
VCC
GND
tf
tr
DATA INPUT
A OR B
OUTPUT
YA OR YB
10%
90%
10%
90%
tTLH
tPLH
tPHL
tTHL
PIN DESCRIPTIONS
INPUTS
A1, A2, A3, A4, B1, B2, B3, B4
(Pins 2, 4, 6, 8, 11, 13, 15, 17)
Data input pins. Data on these pins appear in noninverted
form on the corresponding Y outputs when the outputs are
enabled.
CONTROLS
Enable A (Pin 1)
Output enable (active–low). When a low level is applied to
this pin, the outputs of the “A” devices are enabled and the
devices function as noninverting buffers. When a high level is
applied, the outputs assume the high–impedance state.
Enable 8 (Pin 19)
Output enable (active–high). When a high level is applied
to this pin, the outputs of the “B” devices are enabled and the
devices function as noninverting buffers. When a low level is
applied, the outputs assume the high–impedance state.
OUTPUTS
YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4
(Pins 18, 16, 14, 12, 9, 7, 5, 3)
Device outputs. Depending upon the state of the output–
enable pins, these outputs are either noninverting outputs or
high–impedance outputs.