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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MC74HC175ADG |
| 寤犲晢锛� | ON Semiconductor |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 6/11闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC FLIP FLOP QUAD TYPE D 16-SOIC |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 48 |
| 绯诲垪锛� | 74HC |
| 鍔熻兘锛� | 寰�(f霉)浣� |
| 椤炲瀷锛� | D 鍨嬬附绶� |
| 杓稿嚭椤炲瀷锛� | 宸垎 |
| 鍏冧欢鏁�(sh霉)锛� | 1 |
| 姣忓€�(g猫)鍏冧欢鐨勪綅鍏冩暩(sh霉)锛� | 4 |
| 闋荤巼 - 鏅�(sh铆)閻橈細 | 35MHz |
| 寤堕伈鏅�(sh铆)闁� - 鍌宠几锛� | 28ns |
| 瑙哥櫦(f膩)鍣ㄩ鍨嬶細 | 姝ｉ倞娌� |
| 杓稿嚭闆绘祦楂�锛屼綆锛� | 5.2mA锛�5.2mA |
| 闆绘簮闆诲锛� | 2 V ~ 6 V |
| 宸ヤ綔婧害锛� | -55°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 16-SOIC锛�0.154"锛�3.90mm 瀵級 |
| 鍖呰锛� | 绠′欢 |
| 鍏跺畠鍚嶇ū锛� | MC74HC175ADG-ND MC74HC175ADGOS |
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)鐣�(d膩ng)鍓嶇6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)
MC74HC175A
http://onsemi.com
4
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Unit
Guaranteed Limit
VCC
V
Test Conditions
Parameter
Symbol
Unit
v 125_C
v 85_C
鈥� 55 to
25_C
VCC
V
Test Conditions
Parameter
Symbol
VOL
Maximum LowLevel Output
Voltage
Vin = VIH or VIL
|Iout| v 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
V
Vin = VIH or VIL
|Iout| v 2.4 mA
|Iout| v 4.0 mA
|Iout| v 5.2 mA
3.0
4.5
6.0
0.26
0.33
0.40
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
卤 0.1
卤 1.0
卤 1.0
mA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 mA
6.0
4
40
160
mA
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
鈥� 55 to
25_C
v 85_C
v 125_C
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
3.0
4.5
6.0
6
10
30
35
4.8
8.0
24
28
4
6
20
24
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
2.0
3.0
4.5
6.0
150
75
26
22
190
90
32
28
225
110
38
33
ns
tPHL
Maximum Propagation Delay, Reset to Q or Q
(Figures 2 and 4)
2.0
3.0
4.5
6.0
125
70
22
19
155
85
27
24
190
110
34
30
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
Cin
Maximum Input Capacitance
鈥�
10
10
10
pF
CPD
Power Dissipation Capacitance (Per FlipFlop)*
Typical @ 25掳C, VCC = 5.0 V
pF
35
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC.
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
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| MC74HC175ADR2 | 鍔熻兘鎻忚堪:瑙哥櫦(f膩)鍣� 2-6V CMOS Quad RoHS:鍚� 鍒堕€犲晢:Texas Instruments 闆昏矾鏁�(sh霉)閲�:2 閭忚集绯诲垪:SN74 閭忚集椤炲瀷:D-Type Flip-Flop 妤垫€�:Inverting, Non-Inverting 杓稿叆椤炲瀷:CMOS 杓稿嚭椤炲瀷: 鍌虫挱寤堕伈鏅�(sh铆)闁�:4.4 ns 楂橀浕骞宠几鍑洪浕娴�:- 16 mA 浣庨浕骞宠几鍑洪浕娴�:16 mA 闆绘簮闆诲-鏈€澶�:5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:X2SON-8 灏佽:Reel |
| MC74HC175ADR2G | 鍔熻兘鎻忚堪:瑙哥櫦(f膩)鍣� 2-6V CMOS Quad D-Type Clock Reset RoHS:鍚� 鍒堕€犲晢:Texas Instruments 闆昏矾鏁�(sh霉)閲�:2 閭忚集绯诲垪:SN74 閭忚集椤炲瀷:D-Type Flip-Flop 妤垫€�:Inverting, Non-Inverting 杓稿叆椤炲瀷:CMOS 杓稿嚭椤炲瀷: 鍌虫挱寤堕伈鏅�(sh铆)闁�:4.4 ns 楂橀浕骞宠几鍑洪浕娴�:- 16 mA 浣庨浕骞宠几鍑洪浕娴�:16 mA 闆绘簮闆诲-鏈€澶�:5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:X2SON-8 灏佽:Reel |
| MC74HC175ADR2G-CUT TAPE | 鍒堕€犲晢:ON 鍔熻兘鎻忚堪:MC74HC175A Series Quad D-type Flip-Flop with Common Clock and Reset - SOIC-16 |
| MC74HC175ADT | 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪:- Bulk |
| MC74HC175ADTR2 | 鍔熻兘鎻忚堪:瑙哥櫦(f膩)鍣� 2-6V CMOS Quad RoHS:鍚� 鍒堕€犲晢:Texas Instruments 闆昏矾鏁�(sh霉)閲�:2 閭忚集绯诲垪:SN74 閭忚集椤炲瀷:D-Type Flip-Flop 妤垫€�:Inverting, Non-Inverting 杓稿叆椤炲瀷:CMOS 杓稿嚭椤炲瀷: 鍌虫挱寤堕伈鏅�(sh铆)闁�:4.4 ns 楂橀浕骞宠几鍑洪浕娴�:- 16 mA 浣庨浕骞宠几鍑洪浕娴�:16 mA 闆绘簮闆诲-鏈€澶�:5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:X2SON-8 灏佽:Reel |
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