參數(shù)資料
型號: MC74HC175AD
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: Quad D Flip-Flop with Common Clock and Reset
中文描述: HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
封裝: SOIC-16
文件頁數(shù): 2/8頁
文件大小: 191K
代理商: MC74HC175AD
MC74HC175A
http://onsemi.com
2
Functional operation should be restricted to the Recommended Operating Conditions.
Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
– 0.5 to VCC + 0.5
V
DC Output Voltage (Referenced to GND)
±
25
V
DC Output Current, per Pin
mA
SOIC Package
500
(Plastic DIP, SOIC or TSSOP Package)
Lead Temperature, 1 mm from Case for 10 Seconds
260
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
500
400
Unit
VCC
Vin, Vout
TA
tr, tf
DC Supply Voltage (Referenced to GND)
0
2.0
6.0
VCC
+ 125
V
DC Input Voltage, Output Voltage (Referenced to GND)
0
1000
V
Operating Temperature, All Package Types
– 55
C
Input Rise and Fall Time
VCC = 4.5 V
VCC = 6.0 V
0
0
ns
Symbol
Parameter
Test Conditions
6.0
6.0
6.0
V
4.2
1.80
5.9
25 C
– 55 to
125 C
4 2
1.80
5.9
Voltage
|Iout|
20
μ
A
3.0
2.1
4.2
1.80
5.9
2.1
3.15
2.1
Maximum Low–Level Input
Voltage
|Iout|
20
μ
A
3.0
0.9
0.9
1.35
0.9
Minimum High–Level Output
Vin = VIH or VIL
|Iout|
20
μ
A
3.98
2.0
3.84
1.9
3.70
1.9
1.9
V
|Iout|
4.5
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND
(Vin or Vout)
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
VCC.
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