參數(shù)資料
型號: MC74HC165ADTR2
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: 8-Bit Serial or Parallel-Input/Serial-Output Shift Register
中文描述: HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PDSO16
封裝: LEADFREE, TSSOP-16
文件頁數(shù): 6/12頁
文件大?。?/td> 112K
代理商: MC74HC165ADTR2
MC74HC165A
http://onsemi.com
6
PIN DESCRIPTIONS
INPUTS
A, B, C, D, E, F, G, H (Pins 11, 12, 13, 14, 3, 4, 5, 6)
Parallel Data inputs. Data on these inputs are
asynchronously entered in parallel into the internal
flip–flops when the Serial Shift/Parallel Load input is low.
SA (Pin 10)
Serial Data input. When the Serial Shift/Parallel Load
input is high, data on this pin is serially entered into the first
stage of the shift register with the rising edge of the Clock.
CONTROL INPUTS
Serial Shift/Parallel Load (Pin 1)
Data–entry control input. When a high level is applied to
this pin, data at the Serial Data input (SA) are shifted into the
register with the rising edge of the Clock. When a low level
is applied to this pin, data at the Parallel Data inputs are
asynchronously loaded into each of the eight internal stages.
Clock, Clock Inhibit (Pins 2, 15)
Clock inputs. These two clock inputs function identically.
Either may be used as an active–high clock inhibit.
However, to avoid double clocking, the inhibit input should
go high only while the clock input is high.
The shift register is completely static, allowing Clock
rates down to DC in a continuous or intermittent mode.
OUTPUTS
Q
H
, Q
H
(Pins 9, 7)
Complementary Shift Register outputs. These pins are the
noninverted and inverted outputs of the eighth stage of the
shift register.
相關(guān)PDF資料
PDF描述
MC74HC165AD 8-Bit Serial or Parallel-Input/Serial-Output Shift Register
MC74HC165ADR2 8-Bit Serial or Parallel-Input/Serial-Output Shift Register
MC74HC165ADT 8-Bit Serial or Parallel-Input/Serial-Output Shift Register
MC74HC165AN 8-Bit Serial or Parallel-Input/Serial-Output Shift Register
MC74HC16xADR2 Presettable Counters
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