參數(shù)資料
型號: MC74HC164ADR2
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: 8-Bit Serial-Input/Parallel-Output Shift Register
中文描述: HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO14
封裝: SOIC-14
文件頁數(shù): 5/8頁
文件大?。?/td> 195K
代理商: MC74HC164ADR2
MC74HC164A
http://onsemi.com
5
PIN DESCRIPTIONS
INPUTS
A1, A2 (Pins 1, 2)
Serial Data Inputs. Data at these inputs determine the data
to be entered into the first stage of the shift register. For a
high level to be entered into the shift register, both A1 and
A2 inputs must be high, thereby allowing one input to be
used as a data–enable input. When only one serial input is
used, the other must be connected to VCC.
Clock (Pin 8)
Shift Register Clock. A positive–going transition on this
pin shifts the data at each stage to the next stage. The shift
register is completely static, allowing clock rates down to
DC in a continuous or intermittent mode.
OUTPUTS
QA – QH (Pins 3, 4, 5, 6, 10, 11, 12, 13)
Parallel Shift Register Outputs. The shifted data is
presented at these outputs in true, or noninverted, form.
CONTROL INPUT
Reset (Pin 9)
Active–Low, Asynchronous Reset Input. A low voltage
applied to this input resets all internal flip–flops and sets
Outputs QA – QH to the low level state.
SWITCHING WAVEFORMS
tf
VCC
GND
90%
50%
10%
tw
tPLH
tPHL
CLOCK
Q
tTLH
tTHL
Figure 1.
RESET
trec
Figure 2.
tr
1/fmax
90%
50%
10%
VCC
GND
VCC
GND
Q
CLOCK
50%
50%
50%
tPHL
tw
A1 OR A2
Figure 3.
VCC
GND
VCC
GND
50%
50%
CLOCK
tsu
th
VALID
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 4. Test Circuit
相關(guān)PDF資料
PDF描述
MC74HC164ADT 8-Bit Serial-Input/Parallel-Output Shift Register
MC74HC164AN 8-Bit Serial-Input/Parallel-Output Shift Register
MC74HC164ADTR2 8-Bit Serial-Input/Parallel-Output Shift Register
MC74HC165A 8-Bit Serial or Parallel-Input/Serial-Output Shift Register
MC74HC165ADTR2 8-Bit Serial or Parallel-Input/Serial-Output Shift Register
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