參數(shù)資料
型號: MC74HC163ADR2
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: Presettable Counters
中文描述: HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
封裝: SOIC-16
文件頁數(shù): 5/16頁
文件大?。?/td> 144K
代理商: MC74HC163ADR2
MC74HC161A, MC74HC163A
http://onsemi.com
5
propagation delays. (2) Enable T or Enable P to Clock setup times and (3) Clock to Enable T or Enable P hold times determine fmax. However,
if Ripple Carry out of each stage is tied to the Clock of the next stage (nonsynchronously clocked) the fmax in the table above is applicable.
See Applications information in this data sheet.
10.For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High–Speed
CMOS Data Book (DL129/D).
Symbol
V
Parameter
Figure
6.0
– 55 to 25 C
85 C
Unit
(HC161A Only)
(50% Duty Cycle)
(Note 9.)
6.0
6.0
6.0
4.5
6.0
16
18
17
18
15
2.0
3.0
4.5
35
20
20
19
20
16
15
28
22
23
21
22
20
12
24
10
Clock to Q
3.0
4.5
75
120
150
4, 10
2.0
3.0
4.5
145
100
185
135
220
150
ns
Maximum Propagation Delay,
Reset to Q (HC161A Only)
5, 10
2.0
3.0
4.5
145
185
135
22
220
ns
ns
tPLH
Maximum Propagation Delay,
Enable T to Ripple Carry Out
6, 10
2.0
3.0
4.5
6.0
110
14
150
115
18
15
190
17
ns
tPHL
4.5
6.0
6, 10
22
18
2.0
3.0
27
22
135
30
25
175
130
210
tPLH
Maximum Propagation Delay,
Clock to Ripple Carry Out
4.5
6.0
4, 10
22
20
2.0
3.0
28
24
120
35
28
160
135
200
tPHL
4.5
4, 10
22
2.0
3.0
26
145
30
185
135
220
tPHL
Maximum Propagation Delay,
Reset to Ripple Carry Out
4.5
6.0
5, 10
15
13
2.0
3.0
19
16
155
22
19
190
140
230
Maximum Output Transition Time,
Any Output
2.0
3.0
Typical @ 25
°
C, VCC = 5.0 V
45
CPD
11.Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
Power Dissipation Capacitance (Per Gate) (Note 11.)
pF
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