參數(shù)資料
型號: MC74HC158AN
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: Quad 2-Input Data Selector/Multiplexer
中文描述: HC/UH SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PDIP16
封裝: 648-08
文件頁數(shù): 5/7頁
文件大?。?/td> 149K
代理商: MC74HC158AN
MC74HC158A
High–Speed CMOS Logic Data
DL129 — Rev 6
3–5
MOTOROLA
PIN DESCRIPTIONS
INPUTS
A0–A3 (Pins 2,5,11,14)
Nibble A inputs. The data present on these pins is trans-
ferred to the outputs when the Select input is at a low level and
the Output Enable input is at a low level. The data is presented
to the outputs in inverted form for the HC158A.
B0–B3 (Pins 3,6,10,13)
Nibble B inputs. The data present on these pins is trans-
ferred to the outputs when the Select input is at a high level and
the Output Enable input is at a low level. The data is presented
to the outputs in inverted form for the HC158A.
OUTPUTS
Y0–Y3 (Pins 4,7,9,12)
Data outputs. The selected input nibble is presented at
these outputs when the Output Enable input is at a low level.
The data present on these pins is in its inverted form for the
HC158A. For the Output Enable input at a high level, the out-
puts are at a high level for the HC158A.
CONTROL INPUTS
Select (Pin 1)
Nibble select. This input determines the data word to be
transferred to the outputs. A low level on this input selects the
A inputs and a high level selects the B inputs.
Output Enable (Pin 15)
Output Enable input. A low level on this input allows the
selected data to be presented at the outputs. A high level on
this input sets all of the outputs to a high level for the HC158A.
Figure 5. Expanded Logic Diagram
2
A0
4
Y0
7
Y1
9
Y2
12
Y3
3
B0
5
A1
6
B1
11
A2
10
B2
14
A3
13
B3
15
Output Enable
1
Select
Data
Outputs
Nibble
Inputs
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