參數(shù)資料
型號: MC74HC10ADR2G
廠商: ON SEMICONDUCTOR
元件分類: 門電路
英文描述: NAND GATE, PDSO14
封裝: LEAD FREE, SOIC-14
文件頁數(shù): 3/8頁
文件大?。?/td> 148K
代理商: MC74HC10ADR2G
MC74HC10A
http://onsemi.com
3
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Test Conditions
VCC
V
Guaranteed Limit
Unit
– 55 to
25_C
v 85_C
v 125_C
VIH
Minimum HighLevel Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 μA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL
Maximum LowLevel Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 μA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
VOH
Minimum HighLevel Output
Voltage
Vin = VIH or VIL
|Iout| v 20 μA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL
|Iout| v 2.4 mA
|Iout| v 4.0 mA
|Iout| v 5.2 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOL
Maximum LowLevel Output
Voltage
Vin = VIH
|Iout| v 20 μA
2.0
4.5
6.0
0.1
V
Vin = VIH or VIL
|Iout| v 2.4 mA
|Iout| v 4.0 mA
|Iout| v 5.2 mA
3.0
4.5
6.0
0.26
0.33
0.40
Iin
Maximum Input Leakage Current Vin = VCC or GND
6.0
± 0.1
± 1.0
μA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 μA
6.0
1
10
40
μA
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
– 55 to
25_C
v 85_C
v 125_C
tPLH,
tPHL
Maximum Propagation Delay, Input A, B, or C to Output Y
(Figures 1 and 2)
2.0
3.0
4.5
6.0
95
45
19
16
120
60
24
20
145
75
29
25
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
Cin
Maximum Input Capacitance
10
pF
CPD
Power Dissipation Capacitance (Per Gate)*
Typical @ 25°C, VCC = 5.0 V
pF
25
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC.
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