參數(shù)資料
型號(hào): MC74F256N
廠(chǎng)商: MOTOROLA INC
元件分類(lèi): 通用總線(xiàn)功能
英文描述: Processor Supervisory Circuits 5-SOT-23 -40 to 85
中文描述: F/FAST SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP16
封裝: 648-08
文件頁(yè)數(shù): 4/4頁(yè)
文件大小: 112K
代理商: MC74F256N
4-126
FAST AND LS TTL DATA
MC54/74F256
AC CHARACTERISTICS
Symbol
Parameter
54/74F
54F
74F
Unit
°
CL = 50 pF
°
CL = 50 pF
°
CL = 50 pF
TA = +25
C
VCC = +5.0 V
TA = –55 to +125
C
VCC = 5.0 V
±
10%
TA = 0 to 70
C
VCC = 5.0 V
±
5%
Min
Max
Min
Max
Min
Max
tPHL
Propagation Delay
E to Qn
4.0
3.0
10.5
7.0
4.0
3.0
13
8.5
4.0
3.0
12
7.5
ns
tPLH
tPHL
Propagation Delay
Dn to Qn
3.5
3.0
9.0
7.0
3.5
2.5
11.5
8.5
3.5
2.5
10
7.5
ns
tPLH
tPHL
Propagation Delay
An to Qn
3.5
4.0
14
9.5
3.5
4.0
15.5
11
3.5
4.0
14.5
10
ns
tPLH
tPHL
Propagation Delay
MR to Qn
5.0
9.0
4.5
11.5
4.5
10
ns
AC OPERATING REQUIREMENTS
Symbol
Parameter
54/74F
54F
74F
Unit
VCC = +5.0 V
VCC = 5.0 V
±
10%
VCC = 5.0 V
±
5%
TA = +25
°
C
TA = –55 to +125
°
C
TA = 0 to 70
°
C
Min
Max
Min
Max
Min
Max
ts(L)
Setup Time, HIGH or LOW
Dn to E
4.0
4.0
5.0
5.0
4.0
4.0
ns
ts(H)
th(L)
Hold Time, HIGH or LOW
Dn to E
2.0
2.0
2.0
2.0
2.0
2.0
ns
th(H)
ts(L)
A to E(a)
4.0
4.0
4.0
4.0
4.0
4.0
ns
ts(H)
Setup Time, HIGH or LOW
th(L)
A to E(b)
0
0
0
0
0
0
ns
th(H)
Hold Time HIGH or LOW
tW
tW
NOTES:
1. The Address to Enable setup time is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch is
1.
addressed and the other latches are not affected.
2. The Address to Enable hold time is the time after the LOW-to-HIGH Enable transition that the Address must be stable so that the correct latch is addressed
1.
and the other latches are not affected.
E Pulse Width
4.0
4.0
4.0
ns
MR Pulse Width
4.0
4.0
4.0
ns
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