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參數(shù)資料
| 型號： | MC74F161AD |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Processor Supervisory Circuits 5-SOT-23 -40 to 85 |
| 中文描述： | F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 179K |
| 代理商： | MC74F161AD |
4-131
FAST AND LS TTL DATA
MC74F161A
MC74F163A
NOTE:
This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
LOGIC DIAGRAM
FUNCTIONAL DESCRIPTION
The MC74F161A and MC74F163A count in modulo-16
binary sequence. From state 15 (HHHH) they increment to
state 0 (LLLL). The clock inputs of all flip-flops are driven in
parallel through a clock buffer. Thus all changes of the Q out-
puts (except due to Master Reset of the MC74F161A) occur
as a result of, and synchronous with, the LOW-to-HIGH transi-
tion of the CP input signal. The circuits have four fundamental
modes of operation, in order of precedence: asynchronous re-
set (MC74F161A), synchronous reset (MC74F163A), parallel
load, count-up and hold. Five control inputs
Master Reset
(MR, MC74F161A), Synchronous Reset (SR, MC74F163A),
Parallel Enable (PE), Count Enable Parallel (CEP) and Count
Enable Trickle (CET) — determine the mode of operation, as
shown in the Function Table. A LOW signal on MR overrides
all other inputs and asynchronously forces all outputs LOW. A
LOW signal on SR overrides counting and parallel loading
and allows all outputs to go LOW on the next rising edge of
CP. A LOW signal on PE overrides counting and allows infor-
mation on the Parallel Data (Pn) inputs to be loaded into the
flip-flops on the next rising edge of CP. With PE and MR
(MC74F161A) or SR (MC74F163A) HIGH, CEP and CET per-
mit counting when both are HIGH. Conversely, a LOW signal
on either CEP or CET inhibits counting.
The MC74F161A and MC74F163A use D-type edge-trig-
gered flip-flops and changing the SR, PE, CEP, and CET in-
puts when the CP is in either state does not cause errors, pro-
vided that the recommended setup and hold times, with
respect to the rising edge of CP, are observed.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC74F161AJ | Processor Supervisory Circuits 5-SOT-23 -40 to 85 |
| MC74F161AN | Processor Supervisory Circuits 5-SOT-23 -40 to 85 |
| MC74F163A | Supply Voltage Supervisor w/Watchdog input and manual reset 5-SOT-23 -40 to 85 |
| MC74F164 | Supply Voltage Supervisor w/Watchdog input and manual reset 5-SOT-23 -40 to 85 |
| MC74F164D | Supply Voltage Supervisor w/Watchdog input and manual reset 5-SOT-23 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC74F161ADR2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:ON Semiconductor 功能描述: |
| MC74F161AM | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:ON Semiconductor 功能描述: |
| MC74F161AML | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:ON Semiconductor 功能描述: |
| MC74F161AN | 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
| MC74F161ANMOT88 | 制造商:Motorola 功能描述:74F161N |
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