參數(shù)資料
型號: MC74ACT377NG
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: Octal D Flip−Flop with Clock Enable
中文描述: ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP20
封裝: LEAD FREE, PLASTIC, DIP-20
文件頁數(shù): 1/10頁
文件大?。?/td> 131K
代理商: MC74ACT377NG
Semiconductor Components Industries, LLC, 2006
December, 2006 Rev. 9
1
Publication Order Number:
MC74AC377/D
MC74AC377, MC74ACT377
Octal D FlipFlop with
Clock Enable
The MC74AC377/74ACT377 has eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. The common
buffered Clock (CP) input loads all flip-flops simultaneously, when
the Clock Enable (CE) is LOW. The register is fully edge-triggered.
The state of each D input, one setup time before the LOW-to-HIGH
clock transition, is transferred to the corresponding flip-flop’s Q
output. The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
Features
Ideal for Addressable Register Applications
Clock Enable for Address and Data Synchronization Applications
Eight Edge-Triggered D Flip-Flops
Buffered Common Clock
Outputs Source/Sink 24 mA
See MC74AC273 for Master Reset Version
See MC74AC373 for Transparent Latch Version
See MC74AC374 for 3-State Version
ACT377 Has TTL Compatible Inputs
MSL = 1 for all Surface Mount
Chip Complexity: 292 FETs or 73 Gates
PbFree Packages are Available
19
20
18
17
16
15
14
2
1
3
4
5
6
7
V
CC
13
8
12
9
11
10
O
7
D
7
D
6
O
6
O
5
D
5
D
4
O
4
CP
CE
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
Figure 1. Pinout: 20Lead Packages Conductors
(Top View)
PIN NAMES
PIN
FUNCTION
D
0
D
7
Data Inputs
CE
Clock Enable (Active LOW)
Q
0
Q
7
Data Outputs
CP
Clock Pulse Input
Figure 2. Logic Symbol
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CP
CE
http://onsemi.com
SOIC20W
DW SUFFIX
CASE 751D
TSSOP20
DT SUFFIX
CASE 948E
SOEIAJ20
M SUFFIX
CASE 967
1
1
1
PDIP20
N SUFFIX
CASE 738
1
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
See general marking information in the device marking
section on page 7 of this data sheet.
DEVICE MARKING INFORMATION
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