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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MC74AC373DTR2 |
| 寤犲晢锛� | ON Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 5/12闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC LATCH OCT TRANSP 3ST 20-TSSOP |
| 鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� | Product Obsolescence 24/Jan/2011 |
| 妯欐簴鍖呰锛� | 2,500 |
| 绯诲垪锛� | 74AC |
| 閭忚集椤炲瀷锛� | D 鍨嬮€忔槑閹栧瓨鍣� |
| 闆昏矾锛� | 8:8 |
| 杓稿嚭椤炲瀷锛� | 涓夋厠(t脿i) |
| 闆绘簮闆诲锛� | 2 V ~ 6 V |
| 鐛ㄧ珛闆昏矾锛� | 1 |
| 寤堕伈鏅傞枔 - 鍌宠几锛� | 7ns |
| 杓稿嚭闆绘祦楂橈紝浣庯細 | 24mA锛�24mA |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 20-TSSOP锛�0.173"锛�4.40mm 瀵級 |
| 渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 20-TSSOP |
| 鍖呰锛� | 甯跺嵎 (TR) |
MC74AC373, MC74ACT373
http://onsemi.com
2
TRUTH TABLE
Inputs
Outputs
OE
LE
Dn
On
H
X
Z
L
H
L
H
L
X
O0
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O0 = Previous O0 before LOW-to-HIGH Transition of Clock
FUNCTIONAL DESCRIPTION
The MC74AC373/74ACT373 contains eight Dtype
latches with 3state standard outputs. When the Latch
Enable (LE) input is HIGH, data on the Dn inputs enters the
latches. In this condition the latches are transparent, i.e., a
latch output will change state each time its D input changes.
When LE is LOW, the latches store the information that was
present on the D inputs a setup time preceding the
HIGHtoLOW transition of LE. The 3-state standard
outputs are controlled by the Output Enable (OE) input.
When OE is LOW, the standard outputs are in the 2state
mode. When OE is HIGH, the standard outputs are in the
high impedance mode but this does not interfere with
entering new data into the latches.
Figure 3. Logic Diagram
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D1
D2
D3
D4
D5
D6
D7
LE
OE
D0
NOTE:
This diagram is provided only for the understanding of logic operations and
should not be used to estimate propagation delays.
鐩搁棞PDF璩囨枡 |
PDF鎻忚堪 |
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| MC74AC259MG | IC LATCH ADDRESS 8BIT 16-SOEIAJ |
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| MC74AC259D | IC LATCH ADDRESS 8BIT 16-SOIC |
| OSTVM053552 | TERM BLOCK PLUG 3.81MM 5POS |
鐩搁棞浠ｇ悊鍟�/鎶€琛撳弮鏁�(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MC74AC373DTR2G | 鍔熻兘鎻忚堪:闁夐帠 2-6V Octal Transparent RoHS:鍚� 鍒堕€犲晢:Micrel 闆昏矾鏁�(sh霉)閲�:1 閭忚集椤炲瀷:CMOS 閭忚集绯诲垪:TTL 妤垫€�:Non-Inverting 杓稿嚭绶氳矾鏁�(sh霉)閲�:9 楂橀浕骞宠几鍑洪浕娴�: 浣庨浕骞宠几鍑洪浕娴�: 鍌虫挱寤堕伈鏅傞枔: 闆绘簮闆诲-鏈€澶�:12 V 闆绘簮闆诲-鏈€灏�:5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:SOIC-16 灏佽:Reel |
| MC74AC373DW | 鍔熻兘鎻忚堪:闁夐帠 2-6V Octal RoHS:鍚� 鍒堕€犲晢:Micrel 闆昏矾鏁�(sh霉)閲�:1 閭忚集椤炲瀷:CMOS 閭忚集绯诲垪:TTL 妤垫€�:Non-Inverting 杓稿嚭绶氳矾鏁�(sh霉)閲�:9 楂橀浕骞宠几鍑洪浕娴�: 浣庨浕骞宠几鍑洪浕娴�: 鍌虫挱寤堕伈鏅傞枔: 闆绘簮闆诲-鏈€澶�:12 V 闆绘簮闆诲-鏈€灏�:5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:SOIC-16 灏佽:Reel |
| MC74AC373DWG | 鍔熻兘鎻忚堪:闁夐帠 2-6V Octal Transparent RoHS:鍚� 鍒堕€犲晢:Micrel 闆昏矾鏁�(sh霉)閲�:1 閭忚集椤炲瀷:CMOS 閭忚集绯诲垪:TTL 妤垫€�:Non-Inverting 杓稿嚭绶氳矾鏁�(sh霉)閲�:9 楂橀浕骞宠几鍑洪浕娴�: 浣庨浕骞宠几鍑洪浕娴�: 鍌虫挱寤堕伈鏅傞枔: 闆绘簮闆诲-鏈€澶�:12 V 闆绘簮闆诲-鏈€灏�:5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:SOIC-16 灏佽:Reel |
| MC74AC373DWR2 | 鍔熻兘鎻忚堪:闁夐帠 2-6V Octal RoHS:鍚� 鍒堕€犲晢:Micrel 闆昏矾鏁�(sh霉)閲�:1 閭忚集椤炲瀷:CMOS 閭忚集绯诲垪:TTL 妤垫€�:Non-Inverting 杓稿嚭绶氳矾鏁�(sh霉)閲�:9 楂橀浕骞宠几鍑洪浕娴�: 浣庨浕骞宠几鍑洪浕娴�: 鍌虫挱寤堕伈鏅傞枔: 闆绘簮闆诲-鏈€澶�:12 V 闆绘簮闆诲-鏈€灏�:5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:SOIC-16 灏佽:Reel |
| MC74AC373DWR2G | 鍔熻兘鎻忚堪:闁夐帠 2-6V Octal Transparent RoHS:鍚� 鍒堕€犲晢:Micrel 闆昏矾鏁�(sh霉)閲�:1 閭忚集椤炲瀷:CMOS 閭忚集绯诲垪:TTL 妤垫€�:Non-Inverting 杓稿嚭绶氳矾鏁�(sh霉)閲�:9 楂橀浕骞宠几鍑洪浕娴�: 浣庨浕骞宠几鍑洪浕娴�: 鍌虫挱寤堕伈鏅傞枔: 闆绘簮闆诲-鏈€澶�:12 V 闆绘簮闆诲-鏈€灏�:5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:SOIC-16 灏佽:Reel |
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