Dn O" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� MC74AC373DTR2
寤�(ch菐ng)鍟嗭細 ON Semiconductor
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 5/12闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC LATCH OCT TRANSP 3ST 20-TSSOP
鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� Product Obsolescence 24/Jan/2011
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 2,500
绯诲垪锛� 74AC
閭忚集椤�(l猫i)鍨嬶細 D 鍨嬮€忔槑閹栧瓨鍣�
闆昏矾锛� 8:8
杓稿嚭椤�(l猫i)鍨嬶細 涓夋厠(t脿i)
闆绘簮闆诲锛� 2 V ~ 6 V
鐛�(d煤)绔嬮浕璺細 1
寤堕伈鏅�(sh铆)闁� - 鍌宠几锛� 7ns
杓稿嚭闆绘祦楂橈紝浣庯細 24mA锛�24mA
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤�(l猫i)鍨嬶細 琛ㄩ潰璨艰
灏佽/澶栨锛� 20-TSSOP锛�0.173"锛�4.40mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 20-TSSOP
鍖呰锛� 甯跺嵎 (TR)
MC74AC373, MC74ACT373
http://onsemi.com
2
TRUTH TABLE
Inputs
Outputs
OE
LE
Dn
On
H
X
Z
L
H
L
H
L
X
O0
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O0 = Previous O0 before LOW-to-HIGH Transition of Clock
FUNCTIONAL DESCRIPTION
The MC74AC373/74ACT373 contains eight Dtype
latches with 3state standard outputs. When the Latch
Enable (LE) input is HIGH, data on the Dn inputs enters the
latches. In this condition the latches are transparent, i.e., a
latch output will change state each time its D input changes.
When LE is LOW, the latches store the information that was
present on the D inputs a setup time preceding the
HIGHtoLOW transition of LE. The 3-state standard
outputs are controlled by the Output Enable (OE) input.
When OE is LOW, the standard outputs are in the 2state
mode. When OE is HIGH, the standard outputs are in the
high impedance mode but this does not interfere with
entering new data into the latches.
Figure 3. Logic Diagram
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D1
D2
D3
D4
D5
D6
D7
LE
OE
D0
NOTE:
This diagram is provided only for the understanding of logic operations and
should not be used to estimate propagation delays.
鐩搁棞(gu膩n)PDF璩囨枡
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MC74AC373DTR2G 鍔熻兘鎻忚堪:闁夐帠 2-6V Octal Transparent RoHS:鍚� 鍒堕€犲晢:Micrel 闆昏矾鏁�(sh霉)閲�:1 閭忚集椤�(l猫i)鍨�:CMOS 閭忚集绯诲垪:TTL 妤垫€�:Non-Inverting 杓稿嚭绶�(xi脿n)璺暩(sh霉)閲�:9 楂橀浕骞宠几鍑洪浕娴�: 浣庨浕骞宠几鍑洪浕娴�: 鍌虫挱寤堕伈鏅�(sh铆)闁�: 闆绘簮闆诲-鏈€澶�:12 V 闆绘簮闆诲-鏈€灏�:5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:SOIC-16 灏佽:Reel
MC74AC373DW 鍔熻兘鎻忚堪:闁夐帠 2-6V Octal RoHS:鍚� 鍒堕€犲晢:Micrel 闆昏矾鏁�(sh霉)閲�:1 閭忚集椤�(l猫i)鍨�:CMOS 閭忚集绯诲垪:TTL 妤垫€�:Non-Inverting 杓稿嚭绶�(xi脿n)璺暩(sh霉)閲�:9 楂橀浕骞宠几鍑洪浕娴�: 浣庨浕骞宠几鍑洪浕娴�: 鍌虫挱寤堕伈鏅�(sh铆)闁�: 闆绘簮闆诲-鏈€澶�:12 V 闆绘簮闆诲-鏈€灏�:5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:SOIC-16 灏佽:Reel
MC74AC373DWG 鍔熻兘鎻忚堪:闁夐帠 2-6V Octal Transparent RoHS:鍚� 鍒堕€犲晢:Micrel 闆昏矾鏁�(sh霉)閲�:1 閭忚集椤�(l猫i)鍨�:CMOS 閭忚集绯诲垪:TTL 妤垫€�:Non-Inverting 杓稿嚭绶�(xi脿n)璺暩(sh霉)閲�:9 楂橀浕骞宠几鍑洪浕娴�: 浣庨浕骞宠几鍑洪浕娴�: 鍌虫挱寤堕伈鏅�(sh铆)闁�: 闆绘簮闆诲-鏈€澶�:12 V 闆绘簮闆诲-鏈€灏�:5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:SOIC-16 灏佽:Reel
MC74AC373DWR2 鍔熻兘鎻忚堪:闁夐帠 2-6V Octal RoHS:鍚� 鍒堕€犲晢:Micrel 闆昏矾鏁�(sh霉)閲�:1 閭忚集椤�(l猫i)鍨�:CMOS 閭忚集绯诲垪:TTL 妤垫€�:Non-Inverting 杓稿嚭绶�(xi脿n)璺暩(sh霉)閲�:9 楂橀浕骞宠几鍑洪浕娴�: 浣庨浕骞宠几鍑洪浕娴�: 鍌虫挱寤堕伈鏅�(sh铆)闁�: 闆绘簮闆诲-鏈€澶�:12 V 闆绘簮闆诲-鏈€灏�:5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:SOIC-16 灏佽:Reel
MC74AC373DWR2G 鍔熻兘鎻忚堪:闁夐帠 2-6V Octal Transparent RoHS:鍚� 鍒堕€犲晢:Micrel 闆昏矾鏁�(sh霉)閲�:1 閭忚集椤�(l猫i)鍨�:CMOS 閭忚集绯诲垪:TTL 妤垫€�:Non-Inverting 杓稿嚭绶�(xi脿n)璺暩(sh霉)閲�:9 楂橀浕骞宠几鍑洪浕娴�: 浣庨浕骞宠几鍑洪浕娴�: 鍌虫挱寤堕伈鏅�(sh铆)闁�: 闆绘簮闆诲-鏈€澶�:12 V 闆绘簮闆诲-鏈€灏�:5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:SOIC-16 灏佽:Reel