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參數(shù)資料
| 型號(hào)： | MC74AC299 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | 8-INPUT UNIVERSAL SHIFT/STORAGE REGISTER WITH COMMON PARALLEL I/O PINS |
| 中文描述： | 8輸入通用移位/存儲(chǔ)通用并行I / O引腳注冊(cè) |
| 文件頁(yè)數(shù)： | 3/10頁(yè) |
| 文件大小： | 219K |
| 代理商： | MC74AC299 |
MC74AC299 MC74ACT299
5-3
FACT DATA
FUNCTIONAL DESCRIPTION
The MC74AC299/74ACT299 contains eight edge-triggered
D-type flip-flops and the interstage logic necessary to perform
synchronous shift left, shift right, parallel load and hold
operations. The type of operation is determined by S0 and S1,
as shown in the Truth Table. All flip-flop outputs are brought out
through 3-state buffers to separate I/O pins that also serve as
data inputs in the parallel load mode. Q0 and Q7 are also
brought out on other pins for expansion in serial shifting of
longer words.
A LOW signal on MR overrides the Select and CP inputs
and resets the flip-flops. All other state changes are initiated
by the rising edge of the clock. Inputs can change when the
clock is in either state provided only that the recommended
setup and hold times, relative to the rising edge of CP, are
observed.
A HIGH signal on either OE1 or OE2 disables the 3-state
buffers and puts the I/O pins in the high impedance state. In
this condition the shift, hold, load and reset operations can still
occur. The 3-state buffers are also disabled by HIGH signals
on both S0 and S1 in preparation for a parallel load operation.
TRUTH TABLE
Inputs
Response
MR
S1
X
H
L
H
L
S0
X
H
H
L
L
CP
L
H
H
H
H
X
Asynchronous Reset; Q0–Q7 = LOW
Parallel Load; I/On
Shift Rights; DS0
Shift Left; DS7
Q7, Q7
Hold
Qn
Q0, Q0
Q1, etc.
Q6, etc.
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
Vin
Vout
Iin
Iout
ICC
Tstg
DC Supply Voltage (Referenced to GND)
–0.5 to +7.0
V
DC Input Voltage (Referenced to GND)
–0.5 to VCC +0.5
–0.5 to VCC +0.5
±
20
V
DC Output Voltage (Referenced to GND)
V
DC Input Current, per Pin
mA
DC Output Sink/Source Current, per Pin
±
50
mA
DC VCC or GND Current per Output Pin
Storage Temperature
±
50
mA
–65 to +150
°
C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended
Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
′
AC
2.0
5.0
6.0
V
′
ACT
4.5
5.0
5.5
Vin, Vout
DC Input Voltage, Output Voltage (Ref. to GND)
0
VCC
V
Input Rise and Fall Time (Note 1)
′
AC Devices except Schmitt Inputs
AC Devices exce t Schmitt In uts
d F ll Ti
(N t 1)
VCC @ 3.0 V
VCC @ 4.5 V
150
tr, tf
40
ns/V
VCC @ 5.5 V
VCC @ 4.5 V
VCC @ 5.5 V
25
t tf
tr, tf
Input Rise and Fall Time (Note 2)
′
ACT Devices except Schmitt Inputs
10
ns/V
8.0
TJ
TA
IOH
IOL
Junction Temperature (PDIP)
140
°
C
Operating Ambient Temperature Range
–40
25
85
°
C
Output Current — High
–24
mA
Output Current — Low
24
mA
1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
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