參數(shù)資料
型號: MC7457RX1000LC
廠商: Freescale Semiconductor
文件頁數(shù): 27/71頁
文件大小: 0K
描述: IC MPU RISC 32BIT 483FCCBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC74xx
處理器類型: 32-位 MPC74xx PowerPC
速度: 1.0GHz
電壓: 1.3V
安裝類型: 表面貼裝
封裝/外殼: 483-BCBGA,F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝: 483-FCCBGA(29x29)
包裝: 托盤
Electrical and Thermal Characteristics
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
Freescale Semiconductor
33
Figure 12 shows the L3 bus timing diagrams for the MPC7457 interfaced to PB2 or Late Write SRAMs.
Figure 12. L3 Bus Timing Diagrams for Late Write or PB2 SRAMs
5.2.5
IEEE 1149.1 AC Timing Specifications
Table 15 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 14 through
Table 15. JTAG AC Timing Specifications (Independent of SYSCLK) 1
At recommended operating conditions. See Table 4.
Parameter
Symbol
Min
Max
Unit
Notes
TCK frequency of operation
fTCLK
033.3
MHz
TCK cycle time
tTCLK
30
ns
TCK clock pulse width measured at 1.4 V
tJHJL
15
ns
TCK rise and fall times
tJR and tJF
02
ns
TRST assert time
tTRST
25
ns
2
Input setup times:
Boundary-scan data
TMS, TDI
tDVJH
tIVJH
4
0
ns
3
Input hold times:
Boundary-scan data
TMS, TDI
tDXJH
tIXJH
20
25
ns
3
L3_ECHO_CLK[0,2]
L3 Data and Data
VM
VM = Midpoint Voltage (GVDD/2)
tL3DVEH
tL3DXEH
Parity Inputs
L3_CLK[0,1]
ADDR, L3_CNTL
VM
tL3CHOV
tL3CHOX
VM
L3DATA WRITE
tL3CHDZ
Outputs
Inputs
L3_ECHO_CLK[1,3]
tL3CHDV
tL3CHDX
tL3CHOZ
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