參數(shù)資料
型號: MC7455ARX733LF
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: RISC Microprocessor Hardware Specifications
中文描述: RISC微處理器硬件規(guī)格
文件頁數(shù): 29/64頁
文件大?。?/td> 1127K
代理商: MC7455ARX733LF
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
Freescale Semiconductor
29
Electrical and Thermal Characteristics
Figure 11
shows the typical connection diagram for the MPC7455 interfaced to PB2 SRAMs, such as the Freescale
MCM63R737, or late write SRAMs, such as the Freescale MCM63R836A.
Figure 11. Typical Synchronous 1-MByte L3 Cache Late Write or PB2 Interface
L3_ADDR[16:0]
L3_CNTL[0]
L3_CNTL[1]
SA[16:0]
SS
SW
K
K
ZZ
G
SRAM 0
DQ[0:17]
DQ[18:36
]
GV
DD
/2
1
GND
GND
SW
SRAM 1
SA[16:0]
GV
DD
/2
1
GND
GND
{L3_DATA[0:15],
{L3_DATA[16:31],
{L3_DATA[32:47],
L3_CLK[0]
L3_CLK[1]
L3_ECHO_CLK[0]
L3_ECHO_CLK[1]
L3_ECHO_CLK[2]
{L3_DATA[48:63],
L3_DP[0:1]}
L3_DP[2:3]}
L3_DP[4:5]}
L3_DP[6:7]}
Denotes
Receive (SRAM
to MPC7455)
Aligned Signals
MPC7455
Denotes
Transmit
(MPC7455 to
SRAM)
Aligned Signals
L3_ECHO_CLK[3]
K
K
SS
ZZ
G
DQ[0:17]
DQ[18:36
]
Note:
1. Or as recommended by SRAM manufacturer for single-ended clocking.
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