參數(shù)資料
型號(hào)： MC7447AVU1000NB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 45/56頁(yè)
文件大?。?/td> 0K
描述： IC MPU RISC 32BIT 360-BGA
標(biāo)準(zhǔn)包裝： 44
系列： MPC74xx
處理器類(lèi)型： 32-位 MPC74xx PowerPC
速度： 1.0GHz
電壓： 1.1V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 360-BCBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 360-FCCBGA（25x25）
包裝： 托盤(pán)
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
5
Features
— Guarantees sequential programming model (precise exception model)
— Monitors all dispatched instructions and retires them in order
— Tracks unresolved branches and flushes instructions after a mispredicted branch
— Retires as many as three instructions per clock cycle
Separate on-chip L1 instruction and data caches (Harvard architecture)
— 32-Kbyte, eight-way set-associative instruction and data caches
— Pseudo least-recently-used (PLRU) replacement algorithm
— 32-byte (eight-word) L1 cache block
— Physically indexed/physical tags
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— Instruction cache can provide four instructions per clock cycle; data cache can provide four
words per clock cycle
— Caches can be disabled in software.
— Caches can be locked in software.
— MESI data cache coherency maintained in hardware
— Separate copy of data cache tags for efficient snooping
— Parity support on cache and tags
— No snooping of instruction cache except for icbi instruction
— Data cache supports AltiVec LRU and transient instructions
— Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word
forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical
double-word forwarding.
Level 2 (L2) cache interface
— On-chip, 512-Kbyte, eight-way set-associative unified instruction and data cache
— Fully pipelined to provide 32 bytes per clock cycle to the L1 caches
— A total 9-cycle load latency for an L1 data cache miss that hits in L2
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— 64-byte, two-sectored line size
— Parity support on cache
Separate memory management units (MMUs) for instructions and data
— 52-bit virtual address, 32- or 36-bit physical address
— Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments
— Memory programmable as write-back/write-through, caching-inhibited/caching-allowed, and
memory coherency enforced/memory coherency not enforced on a page or block basis
— Separate IBATs and DBATs (eight each) also defined as SPRs
— Separate instruction and data translation lookaside buffers (TLBs)
– Both TLBs are 128-entry, two-way set-associative, and use an LRU replacement algorithm.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC7447AVU1000NB 制造商:Freescale Semiconductor 功能描述:Microprocessor
MC7447AVU1167NB 功能描述:微處理器 - MPU A7PM PB FREE RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MC7447AVU1250PC 制造商:Freescale Semiconductor 功能描述:MPU MPC74XX RISC 32BIT 0.13UM 1.25GHZ 1.8V/2.5V 360FCCBGA - Tape and Reel
MC7447AVU1267LB 功能描述:微處理器 - MPU A7PM PB FREE RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MC7447AVU1333LB 功能描述:微處理器 - MPU A7PM PB FREE RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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