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參數(shù)資料
| 型號： | MC7445ARX933LG |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 933 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 56/68頁 |
| 文件大?。?/td> | 1609K |
| 代理商： | MC7445ARX933LG |
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MPC7455 RISC Microprocessor Hardware Specifications
MOTOROLA
Features
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— 64-byte (1M) or 128-byte (2M) sectored line size
— Private memory capability for half (1-Mbyte minimum) or all of the L3 SRAM space
— Supports MSUG2 dual data rate (DDR) synchronous Burst SRAMs, PB2 pipelined
synchronous Burst SRAMs, and pipelined (register-register) late write synchronous Burst
SRAMs
— Supports parity on cache and tags
— Configurable core-to-L3 frequency divisors
— 64-bit external L3 data bus sustains 64 bits per L3 clock cycle
Separate memory management units (MMUs) for instructions and data
— 52-bit virtual address; 32- or 36-bit physical address
— Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments
— Memory programmable as write-back/write-through, caching-inhibited/caching-allowed, and
memory coherency enforced/memory coherency not enforced on a page or block basis
— Separate IBATs and DBATs (eight each) also defined as SPRs
— Separate instruction and data translation lookaside buffers (TLBs)
– Both TLBs are 128-entry, two-way set-associative, and use LRU replacement algorithm
– TLBs are hardware- or software-reloadable (that is, on a TLB miss a page table search is
performed in hardware or by system software)
Efficient data flow
— Although the VR/LSU interface is 128 bits, the L1/L2/L3 bus interface allows up to 256 bits
— The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs
— L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1 cache
— As many as eight outstanding, out-of-order, cache misses are allowed between the L1 data
cache and L2/L3 bus
— As many as 16 out-of-order transactions can be present on the MPX bus
— Store merging for multiple store misses to the same line. Only coherency action taken
(address-only) for store misses merged to all 32 bytes of a cache block (no data tenure
needed).
— Three-entry finished store queue and five-entry completed store queue between the LSU and
the L1 data cache
— Separate additional queues for efficient buffering of outbound data (such as castouts and write
through stores) from the L1 data cache and L2 cache
Multiprocessing support features include the following:
— Hardware-enforced, MESI cache coherency protocols for data cache
— Load/store with reservation instruction pair for atomic memory references, semaphores, and
other multiprocessor operations
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC7447A | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerPC microprocessor |
| MC7447AHX1000LB | 功能描述:微處理器 - MPU APOLO7PM RV1.1 1.3V 105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC7447AHX1000NB | 功能描述:微處理器 - MPU APOLO7PM RV1.1 1.1V 105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC7447AHX1000NBR | 制造商:Freescale Semiconductor 功能描述:MPU MPC74XX RISC 32BIT 0.13UM 1GHZ 1.8V/2.5V 360FCCBGA - Tape and Reel |
| MC7447AHX1000PC | 制造商:Freescale Semiconductor 功能描述:MPU MPC74XX RISC 32BIT 0.13UM 1GHZ 1.8V/2.5V 360FCCBGA - Bulk |
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