Central Processor Unit (CPU)
Instruction Set
M68HC11K Family
Technical Data
MOTOROLA
Central Processor Unit (CPU)
59
INS
Increment
Stack Pointer
SP + 1
SP
INH
31
—
3
————
INX
Increment
Index Register
X
IX + 1
IX
INH
08
—
3
————
—
——
INY
Increment
Index Register
Y
IY + 1
IY
INH
18
08
—
4
————
—
——
JMP (opr)
Jump
EXT
IND,X
IND,Y
7E
6E
18
6E
hh ll
ff
3
4
————
JSR (opr)
Jump to
Subroutine
DIR
EXT
IND,X
IND,Y
9D
BD
AD
18
AD
dd
hh ll
ff
5
6
7
————
LDAA (opr)
Load
Accumulator
A
M
A
A
IMM
A
DIR
A
EXT
A
IND,X
A
IND,Y
86
96
B6
A6
18
A6
ii
dd
hh ll
ff
2
3
4
5
————
0
—
LDAB (opr)
Load
Accumulator
B
M
B
B
IMM
B
DIR
B
EXT
B
IND,X
B
IND,Y
C6
D6
F6
E6
18
E6
ii
dd
hh ll
ff
2
3
4
5
————
0
—
LDD (opr)
Load Double
Accumulator
D
M
A,M + 1 BIMM
DIR
EXT
IND,X
IND,Y
CC
DC
FC
EC
18
EC
jj kk
dd
hh ll
ff
3
4
5
6
————
0
—
LDS (opr)
Load Stack
Pointer
M : M + 1
SP
IMM
DIR
EXT
IND,X
IND,Y
8E
9E
BE
AE
18
AE
jj kk
dd
hh ll
ff
3
4
5
6
————
0
—
LDX (opr)
Load Index
Register
X
M : M + 1
IX
IMM
DIR
EXT
IND,X
IND,Y
CE
DE
FE
EE
CD
EE
jj kk
dd
hh ll
ff
3
4
5
6
————
0
—
LDY (opr)
Load Index
Register
Y
M : M + 1
IY
IMM
DIR
EXT
IND,X
IND,Y
18
CE
18
DE
18
FE
1A
EE
18
EE
jj kk
dd
hh ll
ff
4
5
6
————
0
—
LSL (opr)
Logical Shift
Left
EXT
IND,X
IND,Y
78
68
18
68
hh ll
ff
6
7
————
LSLA
Logical Shift
Left A
AINH
48
—
2
————
LSLB
Logical Shift
Left B
BINH
58
—
2
————
LSLD
Logical Shift
Left Double
INH
05
—
3
————
LSR (opr)
Logical Shift
Right
EXT
IND,X
IND,Y
74
64
18
64
hh ll
ff
6
7
————
0
LSRA
Logical Shift
Right A
AINH
44
—
2
————
0
LSRB
Logical Shift
Right B
BINH
54
—
2
————
0
Table 3-1. Instruction Set (Sheet 4 of 7)
Mnemonic
Operation
Description
Addressing
Instruction
Condition Codes
Mode
Opcode
Operand
Cycles
S
X
H
I
N
Z
V
C
C
0
b7
b0
C
0
b7
b0
C
0
b7
b0
C
0
b7
b0
AB
b7
b0
C
0
b7
b0
C
0
b7
b0
C
0
b7
b0
F
re
e
sc
a
le
S
e
m
ic
o
n
d
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to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
