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| 型號： | MC705P6AMPE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 29/98頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8BIT 4.5K FLASH 28-PDIP |
| 標(biāo)準(zhǔn)包裝： | 13 |
| 系列： | HC05 |
| 核心處理器： | HC05 |
| 芯體尺寸： | 8-位 |
| 速度： | 2.1MHz |
| 連通性： | SIO |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 21 |
| 程序存儲器容量： | 4.5KB（4.5K x 8） |
| 程序存儲器類型： | OTP |
| RAM 容量： | 176 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 28-DIP（0.600"，15.24mm） |
| 包裝： | 管件 |
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Interrupt Types
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
35
5.2 Interrupt Types
The interrupts fall into three categories: reset, software, and hardware.
5.2.1 Reset Interrupt Sequence
The reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner
as shown in Figure 5-1. A low-level input on the RESET pin or internally generated RST signal causes
the program to vector to its starting address which is specified by the contents of memory locations $1FFE
and $1FFF. The I bit in the condition code register is also set. The MCU is configured to a known state
during this type of reset as previously described in Chapter 4 Resets.
5.2.2 Software Interrupt (SWI)
The SWI is an executable instruction. It is also a non-maskable interrupt since it is executed regardless
of the state of the I bit in the CCR. As with any instruction, interrupts pending during the previous
instruction will be serviced before the SWI opcode is fetched. The interrupt service routine address for the
SWI instruction is specified by the contents of memory locations $1FFC and $1FFD.
5.2.3 Hardware Interrupts
All hardware interrupts are maskable by the I bit in the CCR. If the I bit is set, all hardware interrupts
(internal and external) are disabled. Clearing the I bit enables the hardware interrupts. Four hardware
interrupts are explained in the following subsections.
5.2.3.1 External Interrupt (IRQ)
The IRQ/VPP pin drives an asynchronous interrupt to the CPU. An edge detector flip-flop is latched on the
falling edge of IRQ/VPP. If either the output from the internal edge detector flip-flop or the level on the
IRQ/VPP pin is low, a request is synchronized to the CPU to generate the IRQ interrupt. If the LEVEL bit
in the mask option register is clear (edge-sensitive only), the output of the internal edge detector flip-flop
is sampled and the input level on the IRQ/VPP pin is ignored. The interrupt service routine address is
specified by the contents of memory locations $1FFA and $1FFB. If the port A interrupts are enabled by
the MOR, they generate external interrupts identically to the IRQ/VPP pin.
NOTE
The internal interrupt latch is cleared nine internal clock cycles after the
interrupt is recognized (immediately after location $1FFA is read).
Therefore, another external interrupt pulse could be latched during the IRQ
service routine.
Another interrupt will be serviced if the IRQ pin is still in a low state when
the RTI in the service routine is executed.
5.2.3.2 Input Capture Interrupt
The input capture interrupt is generated by the 16-bit timer as described in Chapter 8 Capture/Compare
Timer. The input capture interrupt flag is located in register TSR and its corresponding enable bit can be
found in register TCR. The I bit in the CCR must be clear for the input capture interrupt to be enabled. The
interrupt service routine address is specified by the contents of memory locations $1FF8 and $1FF9.
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