參數(shù)資料
型號： MC705JP7CPE
廠商： Freescale Semiconductor
文件頁數(shù)： 101/164頁
文件大?。?/td> 0K
描述： IC MCU 8BIT 224 BYTES RAM 28PDIP
標(biāo)準(zhǔn)包裝： 13
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SIO
外圍設(shè)備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 22
程序存儲器容量： 6KB（6K x 8）
程序存儲器類型： OTP
RAM 容量： 224 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-DIP（0.600"，15.24mm）
包裝： 管件
Analog Interrupts
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
41
4.9 Analog Interrupts
The analog subsystem can generate the following interrupts:
Voltage on positive input of comparator 1 is greater than the voltage on the negative input of
comparator 1.
Voltage on positive input of comparator 2 is greater than the voltage on the negative input of
comparator 2.
Trigger of the input capture interrupt from the programmable timer as described in 4.7.1 Input
Setting the I bit in the condition code register disables analog subsystem interrupts. The controls for these
interrupts are in the analog subsystem control register (ACR) located at $001D, and the status bits are in
the analog subsystem status register (ASR) located at $001E.
4.9.1 Comparator Input Match Interrupt
A comparator input match interrupt occurs if either compare flag bit (CPF1 or CPF2) in the ASR becomes
set while the comparator interrupt enable bit (CPIE) in the ACR is also set. The CPF1 and CPF2 flag bits
can be reset by writing a one to the corresponding CPFR1 or CPFR2 bits in the ASR. Reset clears these
bits.
4.9.2 Input Capture Interrupt
The analog subsystem can also generate an input capture interrupt through the 16-bit programmable
timer. The input capture can be triggered when there is a match in the input conditions for the voltage
comparator 2. If comparator 2 sets the CP2F flag bit in the ASR and the input capture enable (ICEN) in
the ACR is set, then an input capture will be performed by the programmable timer. If the ICIE enable bit
in the TCR is also set, then an input compare interrupt will occur. Reset clears these bits.
NOTE
For the analog subsystem to generate an interrupt using the input capture
function of the programmable timer, the ICEN enable bit in the ACR, and
the ICIE and IEDG bits in the TCR must all be set.
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MC705JP7CPE 制造商:Freescale Semiconductor 功能描述:IC 8BIT MCU 68HC05 2.1MHZ DIP-28
MC705K1CP 制造商:Motorola Inc 功能描述:16 PIN DIP INTEGRATED CIRCUIT
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MC705P6ACDWE 制造商:Freescale Semiconductor 功能描述:8-Bit Microcontroller IC
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