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    參數(shù)資料
    型號: MC705J1ACDWE
    廠商: Freescale Semiconductor
    文件頁數(shù): 161/162頁
    文件大?。?/td> 0K
    描述: IC MCU 8BIT 1.2K RAM 20-SOIC
    標準包裝: 38
    系列: HC05
    核心處理器: HC05
    芯體尺寸: 8-位
    速度: 4MHz
    外圍設備: POR,WDT
    輸入/輸出數(shù): 14
    程序存儲器容量: 1.2KB(1.2K x 8)
    程序存儲器類型: OTP
    RAM 容量: 64 x 8
    電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
    振蕩器型: 內(nèi)部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
    包裝: 管件
    Technical Data
    MC68HC705J1A — Rev. 4.0
    Computer Operating Properly (COP) Module
    Computer Operating Properly (COP) Module
    7.3 Operation
    Operation of the COP is described in this subsection.
    7.3.1 COP Watchdog Timeout
    Four counter stages at the end of the timer make up the COP watchdog.
    The COP resets the MCU if the timeout period occurs before the COP
    watchdog timer is cleared by application software and the IRQ/VPP pin
    voltage is between VSS and VDD. Periodically clearing the counter starts
    a new timeout period and prevents COP reset. A COP watchdog timeout
    indicates that the software is not executing instructions in the correct
    sequence.
    NOTE:
    The internal clock drives the COP watchdog. Therefore, the COP
    watchdog cannot generate a reset for errors that cause the internal clock
    to stop.
    The COP watchdog depends on a power supply voltage at or above a
    minimum specification and is not guaranteed to protect against
    brownout.
    7.3.2 COP Watchdog Timeout Period
    The COP watchdog timer function is implemented by dividing the output
    of the real-time interrupt circuit (RTI) by eight. The RTI select bits in the
    timer status and control register control RTI output, and the selected
    output drives the COP watchdog. See timer status and control register
    NOTE:
    The minimum COP timeout period is seven times the RTI period. The
    COP is cleared asynchronously with the value in the RTI divider; hence,
    the COP timeout period will vary between 7x and 8x the RTI period.
    7.3.3 Clearing the COP Watchdog
    To clear the COP watchdog and prevent a COP reset, write a logic 0 to
    bit 0 (COPC) of the COP register at location $07F0 (see Figure 7-1).
    F
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    Freescale Semiconductor, Inc.
    For More Information On This Product,
    Go to: www.freescale.com
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