MOTOROLA
MC68QH302 Supplement to the MC68302 Users Manual
23
2.8 SCC Mode Register (SCM)
The QH302 supports Tve protocolsHDLC, UART, V.110, transparent, and QH. Only
SCC1 can run the QH protocol. The SCC mode registers (SCM) determine the protocol to
be run for each SCC. Figure 15 shows the SCM register.
Figure 15. SCM Register
SCM[5D0] are common to each protocol while the mode-speciTc bits SCM[15D6] vary
according to the protocol selected in SCM[1D0]. This register is cleared by reset. See
Table 24 for Teld descriptions.
Descriptions of the speciTc mode settings follow.
2.8.1 HDLC Mode Settings
In HDLC mode, the SCM register is the same as in the 302; see Figure 16.
Figure 16. SCM Register in HDLC Mode
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Mode-Specific Bits
Diag[1:0]
ENR
ENT
Mode[1:0]
Table 24. SCM Field Descriptions
Bits
Name
Description
15–6
—
Mode-specific bits
5–4
Diag[1:0]
Diagnostic mode (same as 302)
3
ENR
Enable receiver
2
ENT
Enable transmitter
1–0
Mode[1:0]
Channel mode
00 = HDLC
01 = UART
10 = V.110
11 = Totally transparent/QH (for SCC1 only)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOF[3:0]
C32
FSE
0
RTE
FLG
ENC
Diag[1:0]
ENR
ENT
00
