參數(shù)資料
型號： MC68MH360ZQ25VL
廠商： Freescale Semiconductor
文件頁數(shù)： 51/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 25MHZ 357-PBGA
標(biāo)準(zhǔn)包裝： 44
系列： M683xx
處理器類型： M683xx 32-位
速度： 25MHz
電壓： 3.3V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 托盤
QMC Supplement
C.3.1.1 Activation Procedure
If no S/T transceiver is active, no TCLK clock is generated. Once the rst transceiver is
activated, it will generate a TCLK signal only if DCL and FSC signals are present as well.
Pseudo DCL and FSC signals generated from one of the baud rate generators (BRG) of the
QUICC32 can be used to generate the TCLK signal. The BRG can generate a clock based
on the QUICC32’s system clock. A divider factor should be chosen so that the BRG
frequency is close to 2.048 MHz. This clock then feeds into the 256-divider circuitry of
Figure C-4 to generate a pseudo DCL and a pseudo FSC.
A multiplexer commanded by the QUICC32 is required to select either the BRG signal or
the TCLK signals of the transceivers to be the clock master generating the DCL and FSC
signals.
When no transceiver is activated, the QUICC32 selects the BRG to be the clock master, and
the S/T interface receives the pseudo DCL and FSC signals. (These two signals are not
synchronized to the network but are not used to sample data.)
As the rst MC145574 is activated, it will be able to generate the TCLK signal; see
Figure C-7. This transceiver will then send an interrupt to the QUICC32 (IRQ3—register
NR3[3]—meaning Info 2 has been received) indicating that the activation process has
begun. The QUICC32 then uses the multiplexer to select the TCLK signal of that
MC145574 to be the clock master.
As shown in Figure C-7 and Figure C-8, the TCLK signal is present before the interruption,
with at least 750
s between the IRQ and the received Info 4. The QUICC32 therefore has
750
s to react to the IRQ and to select the new clock master.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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