參數(shù)資料
型號(hào)： MC68MH360AI25L
廠商： Freescale Semiconductor
文件頁數(shù)： 123/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 25MHZ 240-FQFP
標(biāo)準(zhǔn)包裝： 24
系列： M683xx
處理器類型： M683xx 32-位
速度： 25MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 240-BFQFP
供應(yīng)商設(shè)備封裝： 240-FQFP（32x32）
包裝： 托盤
Chapter 4. QMC Exceptions
Note: For the 68360, the bit numbering is reversed. See Appendix A for more information.
Figure 4-3. SCCM Register
4.3 Interrupt Table Entry
The interrupt table contains information about channel-specic events. Its ags are shown
in Figure 4-4. Note that some bits have no meaning when operating in transparent mode.
For more detailed description on which bits are used in HDLC and transparent operation,
refer to Section 2.4, “Channel-Specic Parameters.” Table 4-2 describes the elds of an
interrupt table entry.
Note: For the 68360, the bit numbering is reversed. See Appendix A for more information.
Figure 4-4. Interrupt Table Entry
01234567
IQOV
GINT
GUN
GOV
0
123456789
10
11
12
13
14
15
V
W
NID
IDL
—
CHANNEL NUMBER
MRF
UN
RXF
BSY
TXB
RXB
RESET:
0
00000 00
00000000
Table 4-2. Interrupt Table Entry Field Descriptions
Field
Name
Description
0
V
Valid bit
0 = Entry is not valid.
1 = Valid entry containing interrupt information.
Upon generating a new entry, the RISC processor sets this bit. The V bit is cleared by the host
immediately after it reads the interrupt ags in this entry (before processing the interrupt). The
V bits in the queue are host-initialized. During the initialization procedure, the host must clear
those bits in all queue entries.
1
W
Wrap bit
0 = This is not the last entry in the circular interrupt table.
1 = This is the last circular interrupt table entry. The next event’s entry is written/read (by RISC/
host) from the address contained in INTBASE.
During initialization, the host must clear all W bits in the queue except the last one which must
be set. The length of the queue is left to the user and can be a maximum of 64 Kbytes.
2
NID
Not idle
0 = No NID event has occurred.
1 = A pattern which is not an idle pattern was identied.
NID interrupts are not generated in transparent mode.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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