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參數(shù)資料
| 型號： | MC68LK332GCPV16 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 82/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT LV GMASK 144-LQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | M683xx |
| 核心處理器： | CPU32 |
| 芯體尺寸： | 32-位 |
| 速度： | 16.78MHz |
| 連通性： | EBI/EMI，SCI，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 15 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 144-LQFP |
| 包裝： | 托盤 |
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MC68332
MOTOROLA
MC68332TS/D
83
IDLE — Idle-Line Detected Flag
0 = SCI receiver did not detect an idle-line condition.
1 = SCI receiver detected an idle-line condition.
IDLE is disabled when RWU in SCCR1 is set. IDLE is set when the SCI receiver detects the idle-line
condition specified by ILT in SCCR1. If cleared, IDLE will not set again until after RDRF is set. RDRF
is set when a break is received, so that a subsequent idle line can be detected.
OR — Overrun Error Flag
0 = RDRF is cleared before new data arrives.
1 = RDRF is not cleared before new data arrives.
OR is set when a new byte is ready to be transferred from the receive serial shifter to the RDR, and
RDRF is still set. Data transfer is inhibited until OR is cleared. Previous data in RDR remains valid, but
data received during overrun condition (including the byte that set OR) is lost.
NF — Noise Error Flag
0 = No noise detected on the received data
1 = Noise occurred on the received data
NF is set when the SCI receiver detects noise on a valid start bit, on any data bit, or on a stop bit. It is
not set by noise on the idle line or on invalid start bits. Each bit is sampled three times. If none of the
three samples are the same logic level, the majority value is used for the received data value, and NF
is set. NF is not set until an entire frame is received and RDRF is set.
FE — Framing Error Flag
0 = No framing error on the received data.
1 = Framing error or break occurred on the received data.
FE is set when the SCI receiver detects a zero where a stop bit was to have occurred. FE is not set until
the entire frame is received and RDRF is set. A break can also cause FE to be set. It is possible to miss
a framing error if RXD happens to be at logic level one at the time the stop bit is expected.
PF — Parity Error Flag
0 = No parity error on the received data
1 = Parity error occurred on the received data
PF is set when the SCI receiver detects a parity error. PF is not set until the entire frame is received and
RDRF is set.
SCDR contains two data registers at the same address. Receive data register (RDR) is a read-only reg-
ister that contains data received by the SCI. The data comes into the receive serial shifter and is trans-
ferred to RDR. Transmit data register (TDR) is a write-only register that contains data to be transmitted.
The data is first written to TDR, then transferred to the transmit serial shifter, where additional format
bits are added before transmission. R[7:0]/T[7:0] contain either the first eight data bits received when
SCDR is read, or the first eight data bits to be transmitted when SCDR is written. R8/T8 are used when
the SCI is configured for 9-bit operation. When it is configured for 8-bit operation, they have no meaning
or effect.
SCDR — SCI Data Register
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15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R8/T8
R7/T7
R6/T6
R5/T5
R4/T4
R3/T3
R2/T2
R1/T1
R0/T0
RESET:
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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