參數(shù)資料
型號(hào): MC68LC302CPU16
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 16.67 MHz, RISC MICROCONTROLLER, PQFP100
封裝: TQFP-100
文件頁(yè)數(shù): 90/182頁(yè)
文件大?。?/td> 618K
代理商: MC68LC302CPU16
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Configuration, Clocking, Low Power Modes, and Internal Memory Map
MOTOROLA
MC68LC302 REFERENCE MANUAL
2-5
Bits 11–0—Base Address
The high address field is contained in bit 11–0 of the BAR. These bits are used to set the
starting address of the dual-port RAM. The address compare logic uses only the most sig-
nificant bits to cause an address match within its block size. Even though A23-20 are sig-
nals are not available, they are driven internally by the core, or driven to zeroes in disable
CPU mode or when HALT has been asserted by an external master.
2.3 SYSTEM CONFIGURATION REGISTERS
A number of entries in the M68000 exception vectors table (located in low RAM) are
reserved for the addresses of system configuration registers (see Table 2-1). These regis-
ters have seven addresses within $0F0-$0FF. The MC68LC302 uses one of the IMP 32-bit
reserved spaces for 3 registers added for the MC68LC302. These registers are used to con-
trol the PLL, clock generation and low power modes. See 2.4 Clock Generation and Low
Power Control.
2.4 CLOCK GENERATION AND LOW POWER CONTROL
The MC68LC302 includes a clock circuit that consists of crystal oscillator drive circuit capa-
ble of driving either an external crystal or accepting an oscillator clock, a PLL clock synthe-
sizer capable of multiplying a low frequency clock or crystal such as a 32-kHz watch crystal
up to the maximum clock rate of each processor, and a low power divider which allows
dynamic gear down and gear up of the system clock for each processor on the fly.
On-Chip Clock Synthesizers (with output system clocks)
—Oscillator Drive Circuits and Pins
—PLL Clock Synthesizer Circuits with Low Power Output Clock Divider Block.
Low Power Control Of IMP
—Slow-Go Modes using PLL Clock Divider Blocks
—Varied Low Power STOP Modes for Optimizing Wake-Up Time to Low Power
Mode Power Consumption: Stand-By, Doze and STOP.
2.4.1 PLL and Oscillator Changes to IMP
The oscillator that was on the MC68302 has been replaced by the new clock synthesizer
described in this section.The registers related to the oscillator have been either removed or
Table 2-1. System Configuration Registers
Address
Name
Width
Description
Reset Value
$0F0
PITR
16
Periodic Interrupt Timer Register
0000
$0F2
BAR
16
Base Address Register
BFFF
$0F4
SCR
24
System Control Register
0000 0F
$0F7
IWUCR
8
IMP Wake-Up Control Register
00
$0F8
IPLCR
16
IMP PLL Control Register
$0FA
IOMCR
8
IMP Operations Mode Control Register
00
$0FB
IPDR
8
IMP Power Down Register
00
$0FC
RES
32
Reserved
相關(guān)PDF資料
PDF描述
MC68LC302CRC20 32-BIT, 20 MHz, RISC MICROCONTROLLER, CPGA132
MC68LC302PU16V 32-BIT, 16.67 MHz, RISC MICROCONTROLLER, PQFP100
MC68LC302RC25B 32-BIT, 25 MHz, RISC MICROCONTROLLER, CPGA132
MC68LC302CPU16B 32-BIT, 16.67 MHz, RISC MICROCONTROLLER, PQFP100
MC68LC302PU16VB 32-BIT, 16.67 MHz, RISC MICROCONTROLLER, PQFP100
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