MOTOROLA
M68040 USER’S MANUAL
7- 47
OWN/PARK,
IMPLICIT
OWNERSHIP,
BGI
Λ
*TSI
*BGI
Λ
*TSI
Λ
*BBI
*ENDCYCLE
Λ
*BBI
*ENDCYCLE
Λ
BBI
Λ
BG
BG*
Λ IBR
SNOOP,
BBO DRIVEN BY
MC68040,
*THREE-STATED
*BG
Λ IBR
ENDCYCLE
*ENDCYCLE
Λ BBI Λ *BG Λ IBR
*ENDCYCLE
Λ BBI Λ *BG Λ *IBR
BG
Λ ENDCYCLE
Λ *TIP
*BG
BBI
Λ *BG Λ IBR Λ TSI
BG
Λ TIP
BBI
Λ *BG Λ *IBR Λ TSI
BG
Λ *ENDCYCLE Λ TIP*
BG
Λ TSI
*BG
Λ TSI Λ *BBI
IDLE,
*BG
Λ *TSI Λ BBI
PROTOCOL
VIOLATION
IBR
BBI
TSI
ENDCYCLE
= Internal bus request signal (see schematic below).
= Bus busy driven by alternate bus master.
= Transfer start as an input, sampled by the MC68040.
= Whatever terminates a bus transaction
whether it is normal, bus error, or retried. Note
that false burst cycles are treated as a line
transaction. False locked transactions
are treated the same as any other bus cycle.
*BBO DRIVEN BY
MC68040,
THREE-STATED
BBO DRIVEN BY
MC68040,
THREE-STATED
BBO DRIVEN BY
MC68040,
*THREE-STATED
D
BB
BBI
Q
BR
BBO
IBR
BCLK
= The 040 may or may not transition if an active bus
cycle is terminated with a bus error, and BG is
asserted.
*
= Indicates the signal is asserted for that device.
Figure 7-30. M68040 Internal Interpretation State Diagram and
External Bus Arbiter Circuit
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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