
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
59
LIRDV—LIR Driven
Refer to
2 Operating Modes
.
CWOM —Port C Wired-OR Mode
Refer to
6 Parallel Input/Output
.
Bit 5 —Not implemented
Always read zero
IRVNE —Internal Read Visibility/Not E
Refer to
2 Operating Modes
.
LSBF —SPI LSB First Enable
0 = SPI data transferred MSB first
1 = SPI data transferred LSB first
SPR2 —SPI Clock (SCK) Rate Select
Adds a divide by four prescaler to SPI clock chain. Refer to SPCR register.
XDV[1:0] —XOUT Clock Divide Select
Refer to
2 Operating Modes
.
OPT2
—System Configuration Options 2
$0038
Bit 7
6
5
4
3
2
1
Bit 0
LIRDV
CWOM
—
IRVNE
LSBF
SPR2
XDV1
XDV0
RESET:
0
0
0
—
0
0
0
0