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參數(shù)資料
| 型號： | MC68L11FC0PU4 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Technical Summary 8-Bit Microcontroller |
| 中文描述： | 8-BIT, MICROCONTROLLER, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁數(shù)： | 30/74頁 |
| 文件大?。?/td> | 513K |
| 代理商： | MC68L11FC0PU4 |
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MOTOROLA
MC68HC11F1/FC0
36
MC68HC11FTS/D
For DDRx bits, 0 = input and 1 = output.
NOTE
When the SPI system is in slave mode, DDD5 has no meaning or effect. When the
SPI system is in master mode, DDD5 determines whether bit 5 of PORTD is an er-
ror detect input (DDD5 = 0) or a general-purpose output (DDD5 = 1). If the SPI sys-
tem is enabled and expects one or more of bits [4:2] to be inputs, those bits will be
inputs regardless of the state of the associated DDR bits. If one or more of bits [4:2]
are expected to be outputs, those bits will be outputs only if the associated DDR
bits are set.
U = Unaffected by rest.
PORTE is an input-only register. Reads return the digital state of the I/O pins, and writes have no effect.
On the MC68HC11F1, port E is shared with the analog-to-digital converter. (The A/D converter is not
present on the MC68HC11FC0.)
GWOM — Port G Wired-OR Mode Option
This bit affects all port G pins together.
0 = Port G outputs are normal CMOS outputs
1 = Port G outputs act as open-drain outputs
NOTES:
1. These bits are not present on the MC68HC11FC0 and will always read zero.
2. This bit is not present on the 64-pin QFP version of the MC68HC11FC0 and will always read zero.
PORTD — Port D Data Register
$x008
Bit 7
654321
Bit 0
0
PD5
PD4
PD3
PD2
PD1
PD0
RESET:
0
IIIIII
Alternate
Function:
—
SS
SCK
MOSI
MISO
TxD
RxD
DDRD — Port D Data Direction Register
$x009
Bit 7
654321
Bit 0
0
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
RESET:
00000000
PORTE — Port E Data
$x00A
Bit 7
654321
Bit 0
PE71
PE6
PE5
PE42
PE3
PE2
PE1
RESET:
UUUUUUUU
Alternate
Function
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
OPT2 — System Configuration Option Register 2
$x038
Bit 7
6
5
4
3
2
1
Bit 0
GWOM
CWOM
CLK4X
LIRDV
—
SPRBYP
—
RESET
0
1
0
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