參數資料
型號: MC68L11D0CFBE2
廠商: Freescale Semiconductor
文件頁數: 42/124頁
文件大小: 0K
描述: IC MCU 8BIT LV 192RAM 44-QFP
標準包裝: 96
系列: HC11
核心處理器: HC11
芯體尺寸: 8-位
速度: 2MHz
連通性: SCI,SPI
外圍設備: POR,WDT
輸入/輸出數: 26
程序存儲器類型: ROMless
RAM 容量: 192 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-QFP
包裝: 托盤
CENTRAL PROCESSING UNIT
3-4
TECHNICAL DATA
When a subroutine is called by a jump to subroutine (JSR) or branch to subroutine
(BSR) instruction, the address of the instruction after the JSR or BSR is automatically
pushed onto the stack, least significant byte first. When the subroutine is finished, a
return from subroutine (RTS) instruction is executed. The RTS pulls the previously
stacked return address from the stack, and loads it into the program counter. Execu-
tion then continues at this recovered return address.
When an interrupt is recognized, the current instruction finishes normally, the return
address (the current value in the program counter) is pushed onto the stack, all of the
CPU registers are pushed onto the stack, and execution continues at the address
specified by the vector for the interrupt. At the end of the interrupt service routine, an
RTI instruction is executed. The RTI instruction causes the saved registers to be pulled
off the stack in reverse order. Program execution resumes at the return address.
There are instructions that push and pull the A and B accumulators and the X and Y
index registers. These instructions are often used to preserve program context. For ex-
ample, pushing accumulator A onto the stack when entering a subroutine that uses ac-
cumulator A, and then pulling accumulator A off the stack just before leaving the
subroutine, ensures that the contents of a register will be the same after returning from
the subroutine as it was before starting the subroutine.
3.1.5 Program Counter (PC)
The program counter, a 16-bit register, contains the address of the next instruction to
be executed. After reset, the program counter is initialized from one of six possible
vectors, depending on operating mode and the cause of reset.
3.1.6 Condition Code Register (CCR)
This 8-bit register contains five condition code indicators (C, V, Z, N, and H), two inter-
rupt masking bits, (IRQ and XIRQ) and a stop disable bit (S). In the M68HC11 CPU,
condition codes are automatically updated by most instructions. For example, load ac-
cumulator A (LDAA) and store accumulator A (STAA) instructions automatically set or
clear the N, Z, and V condition code flags. Pushes, pulls, add B to X (ABX), add B to
Y (ABY), and transfer/exchange instructions do not affect the condition codes. Refer
to Table 3-2, which shows what condition codes are affected by a particular instruc-
tion.
3.1.6.1 Carry/Borrow (C)
The C bit is set if the arithmetic logic unit (ALU) performs a carry or borrow during an
arithmetic operation. The C bit also acts as an error flag for multiply and divide opera-
Table 3-1 Reset Vector Comparison
POR or Pin
Clock Monitor
COP Watchdog
Normal
$FFFE, F
$FFFC, D
$FFFA, B
Test or Boot
$BFFE, F
$BFFC, D
$BFFA, B
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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