參數(shù)資料
型號： MC68L11D0CFB2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP44
封裝： 10 X 10 MM, 2 MM HEIGHT, 0.80 MM PITCH, QFP-44
文件頁數(shù)： 131/131頁
文件大小： 1640K
代理商： MC68L11D0CFB2
MC68HC11D3
TIMING SYSTEM
MOTOROLA
TECHNICAL DATA
9-13
The clock source for the RTI function is a free-running clock that cannot be stopped or
interrupted except by reset. This clock causes the time between successive RTI time-
outs to be a constant that is independent of the software latencies associated with flag
clearing and service. For this reason, an RTI period starts from the previous time-out,
not from when RTIF is cleared.
Every time-out causes the RTIF bit in TFLG2 to be set, and if RTII is set, an interrupt
request is generated. After reset, one entire real-time interrupt period elapses before
the RTIF flag is set for the first time. Refer to the TMSK2, TFLG2, and PACTL regis-
ters.
9.4.1 Timer Interrupt Mask 2 Register
This register contains the real-time interrupt enable bits.
TOI — Timer Overflow Interrupt Enable
RTII — Real-time Interrupt Enable
0 = RTIF interrupts disabled
1 = Interrupt requested when RTIF is set to one
PAOVI — Pulse Accumulator Overflow Interrupt Enable
PAII — Pulse Accumulator Input Edge
NOTE
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in
TMSK2 enable the corresponding interrupt sources.
9.4.1 Timer Interrupt Flag 2 Register
Bits of this register indicate the occurrence of timer system events. Coupled with the
four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate
in either a polled or interrupt driven system. Each bit of TFLG2 corresponds to a bit in
TMSK2 in the same position.
RTR[1:0]
E = 1 MHz
E = 2 MHz
E = 3 MHz
E = X MHz
0 0
0 1
1 0
1 1
2.731 ms
5.461 ms
10.923 ms
21.845 ms
4.096 ms
8.192 ms
16.384 ms
32.768 ms
8.192 ms
16.384 ms
32.768 ms
65.536 ms
(E/213)
(E/214)
(E/215)
(E/216)
TMSK2 — Timer Interrupt Mask 2
$0024
Bit 7
654321
Bit 0
TOI
RTII
PAOVI
PAII
0
PR1
PR0
RESET:
0000000
0
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