參數(shù)資料
型號(hào): MC68HSC705J1ACPE
廠商: Freescale Semiconductor
文件頁數(shù): 144/162頁
文件大?。?/td> 0K
描述: IC MCU 8BIT 64 BYTES RAM 20-PDIP
標(biāo)準(zhǔn)包裝: 18
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 14
程序存儲(chǔ)器容量: 1.2KB(1.2K x 8)
程序存儲(chǔ)器類型: OTP
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
Technical Data
MC68HC705J1A — Rev. 4.0
Low-Power Modes
Low-Power Modes
5.4.2 CPU
The STOP instruction:
Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts
Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the
oscillator stabilization delay.
After exit from stop mode by external interrupt, the I bit remains clear.
After exit from stop mode by reset, the I bit is set.
The WAIT instruction:
Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts
Disables the CPU clock
After exit from wait mode by interrupt, the I bit remains clear.
After exit from wait mode by reset, the I bit is set.
5.4.3 COP Watchdog
The STOP instruction:
Clears the COP watchdog counter
Disables the COP watchdog clock
NOTE:
To prevent the STOP instruction from disabling the COP watchdog,
program the stop-to-wait conversion bit (SWAIT) in the mask option
register to logic 1.
After exit from stop mode by external interrupt, the COP watchdog
counter immediately begins counting from $0000 and continues
counting throughout the oscillator stabilization delay.
NOTE:
Immediately after exiting stop mode by external interrupt, service the
COP to ensure a full COP timeout period.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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