參數(shù)資料
型號: MC68HSC05K0DW
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, MICROCONTROLLER, PDSO16
封裝: SOIC-16
文件頁數(shù): 96/154頁
文件大?。?/td> 1544K
代理商: MC68HSC05K0DW
Technical Data
MC68HC05K0 MC68HC05K1 — Rev. 2.0
46
Interrupts
MOTOROLA
Technical Data
Figure 4-1. External Interrupt Logic
4.3.2.2 PA3–PA0 Pins
The mask option for port A external interrupts enables pins PA3–PA0 to
serve as additional external interrupt sources. The PA3–PA0 pins do not
contain internal Schmitt triggers. An interrupt signal on one of the
PA3–PA0 pins latches an external interrupt request. After completing
the current instruction, the CPU tests these bits:
IRQF bit (IRQ latch)
IRQE bit in the interrupt status and control register
I bit in the condition code register
If both the IRQ latch and the IRQE bit are set and the I bit is clear, the
CPU then begins the interrupt sequence. The CPU clears the IRQ latch
while it fetches the interrupt vector, so that another external interrupt
request can be latched during the interrupt service routine. As soon as
LEVEL-SENSITIVE TRIGGER
PA3
PA2
PA1
IRQ
PA0
IRQ
LATCH
VDD
(MASK OPTION)
RST
IRQ VECTOR FETCH
IRQ STATUS AND CONTROL REGISTER
EXTERNAL
INTERRUPT
REQUEST
IRQE
IRQF
IRQR
PORT A
EXTERNAL INTERRUPTS
ENABLED
(MASK OPTION)
INTERNAL DATA BUS
TO BIH & BIL
INSTRUCTION
PROCESSING
R
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